- # Address to Set/Get to Mailbox in Multicore system\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018\r
- # Address/Value to clear Mailbox in Multicore system\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A\r
+ \r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit \r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # 0x31 = NS | EA | FW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+ \r
+ # Non Secure Access Control Register\r
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+ # 0xC00 = cp10 | cp11\r
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+ \r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
+\r
+ # System Memory (DRAM): These PCDs define the region of in-built system memory\r
+ # Some platforms can get DRAM extensions, these additional regions will be declared\r
+ # to UEFI by ArmPLatformPlib \r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
+\r
+ # Use ClusterId + CoreId to identify the PrimaryCore\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
+ # The Primary Core is ClusterId[0] & CoreId[0] \r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r