- \r
- #\r
- # ARM Security Extension\r
- #\r
- \r
- # Secure Configuration Register\r
- # - BIT0 : NS - Non Secure bit \r
- # - BIT1 : IRQ Handler\r
- # - BIT2 : FIQ Handler\r
- # - BIT3 : EA - External Abort\r
- # - BIT4 : FW - F bit writable\r
- # - BIT5 : AW - A bit writable\r
- # - BIT6 : nET - Not Early Termination\r
- # - BIT7 : SCD - Secure Monitor Call Disable\r
- # - BIT8 : HCE - Hyp Call enable\r
- # - BIT9 : SIF - Secure Instruction Fetch\r
- # 0x31 = NS | EA | FW\r
- gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
- \r
- # Non Secure Access Control Register\r
- # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
- # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
- # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
- # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
- # 0xC00 = cp10 | cp11\r
- gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
- \r
- # System Memory (DRAM): These PCDs define the region of in-built system memory\r
- # Some platforms can get DRAM extensions, these additional regions will be declared\r
- # to UEFI by ArmPLatformPlib \r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r