+\r
+[PcdsFixedAtBuild.ARM]\r
+ # Stack for CPU Cores in Secure Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
+ # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
+ # and PcdCPUCoreSecSecondaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
+\r