UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciResourceSupport.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index 2f713fcee95eb0479e37b87ee8411aebe10ac5c7..8ffd05f327d0b393654e04d2651e12de8357f30e 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -1,14 +1,8 @@
 /** @file\r
 /** @file\r

-  PCI resouces support functions implemntation for PCI Bus module.\r
+  PCI resources support functions implementation for PCI Bus module.\r

 \r
 \r

-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r

 \r
 **/\r
 \r
 \r
 **/\r
 \r


@@ -17,9 +11,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //\r
 // The default policy for the PCI bus driver is NOT to reserve I/O ranges for both ISA aliases and VGA aliases.\r
 //\r
 //\r
 // The default policy for the PCI bus driver is NOT to reserve I/O ranges for both ISA aliases and VGA aliases.\r
 //\r

-BOOLEAN mReserveIsaAliases = FALSE;\r
-BOOLEAN mReserveVgaAliases = FALSE;\r
-BOOLEAN mPolicyDetermined  = FALSE;\r
+BOOLEAN  mReserveIsaAliases = FALSE;\r
+BOOLEAN  mReserveVgaAliases = FALSE;\r
+BOOLEAN  mPolicyDetermined  = FALSE;\r

 \r
 /**\r
   The function is used to skip VGA range.\r
 \r
 /**\r
   The function is used to skip VGA range.\r


@@ -30,8 +24,8 @@ BOOLEAN mPolicyDetermined  = FALSE;
 **/\r
 VOID\r
 SkipVGAAperture (\r
 **/\r
 VOID\r
 SkipVGAAperture (\r

-  OUT UINT64   *Start,\r
-  IN  UINT64   Length\r
+  OUT UINT64  *Start,\r
+  IN  UINT64  Length\r

   )\r
 {\r
   UINT64  Original;\r
   )\r
 {\r
   UINT64  Original;\r


@@ -43,7 +37,7 @@ SkipVGAAperture (
   //\r
   // For legacy VGA, bit 10 to bit 15 is not decoded\r
   //\r
   //\r
   // For legacy VGA, bit 10 to bit 15 is not decoded\r
   //\r

-  Mask        = 0x3FF;\r
+  Mask = 0x3FF;\r

 \r
   Original    = *Start;\r
   StartOffset = Original & Mask;\r
 \r
   Original    = *Start;\r
   StartOffset = Original & Mask;\r


@@ -62,11 +56,10 @@ SkipVGAAperture (
 **/\r
 VOID\r
 SkipIsaAliasAperture (\r
 **/\r
 VOID\r
 SkipIsaAliasAperture (\r

-  OUT UINT64   *Start,\r
-  IN  UINT64   Length\r
+  OUT UINT64  *Start,\r
+  IN  UINT64  Length\r

   )\r
 {\r
   )\r
 {\r

-\r

   UINT64  Original;\r
   UINT64  Mask;\r
   UINT64  StartOffset;\r
   UINT64  Original;\r
   UINT64  Mask;\r
   UINT64  StartOffset;\r


@@ -77,7 +70,7 @@ SkipIsaAliasAperture (
   //\r
   // For legacy ISA, bit 10 to bit 15 is not decoded\r
   //\r
   //\r
   // For legacy ISA, bit 10 to bit 15 is not decoded\r
   //\r

-  Mask        = 0x3FF;\r
+  Mask = 0x3FF;\r

 \r
   Original    = *Start;\r
   StartOffset = Original & Mask;\r
 \r
   Original    = *Start;\r
   StartOffset = Original & Mask;\r


@@ -98,14 +91,14 @@ SkipIsaAliasAperture (
 **/\r
 VOID\r
 InsertResourceNode (\r
 **/\r
 VOID\r
 InsertResourceNode (\r

-  IN OUT PCI_RESOURCE_NODE   *Bridge,\r
-  IN     PCI_RESOURCE_NODE   *ResNode\r
+  IN OUT PCI_RESOURCE_NODE  *Bridge,\r
+  IN     PCI_RESOURCE_NODE  *ResNode\r

   )\r
 {\r
   )\r
 {\r

-  LIST_ENTRY        *CurrentLink;\r
-  PCI_RESOURCE_NODE *Temp;\r
-  UINT64            ResNodeAlignRest;\r
-  UINT64            TempAlignRest;\r
+  LIST_ENTRY         *CurrentLink;\r
+  PCI_RESOURCE_NODE  *Temp;\r
+  UINT64             ResNodeAlignRest;\r
+  UINT64             TempAlignRest;\r

 \r
   ASSERT (Bridge  != NULL);\r
   ASSERT (ResNode != NULL);\r
 \r
   ASSERT (Bridge  != NULL);\r
   ASSERT (ResNode != NULL);\r


@@ -119,8 +112,8 @@ InsertResourceNode (
     if (ResNode->Alignment > Temp->Alignment) {\r
       break;\r
     } else if (ResNode->Alignment == Temp->Alignment) {\r
     if (ResNode->Alignment > Temp->Alignment) {\r
       break;\r
     } else if (ResNode->Alignment == Temp->Alignment) {\r

-      ResNodeAlignRest  = ResNode->Length & ResNode->Alignment;\r
-      TempAlignRest     = Temp->Length & Temp->Alignment;\r
+      ResNodeAlignRest = ResNode->Length & ResNode->Alignment;\r
+      TempAlignRest    = Temp->Length & Temp->Alignment;\r

       if ((ResNodeAlignRest == 0) || (ResNodeAlignRest >= TempAlignRest)) {\r
         break;\r
       }\r
       if ((ResNodeAlignRest == 0) || (ResNodeAlignRest >= TempAlignRest)) {\r
         break;\r
       }\r


@@ -134,11 +127,11 @@ InsertResourceNode (
 \r
 /**\r
   This routine is used to merge two different resource trees in need of\r
 \r
 /**\r
   This routine is used to merge two different resource trees in need of\r

-  resoure degradation.\r
+  resource degradation.\r

 \r
   For example, if an upstream PPB doesn't support,\r
   prefetchable memory decoding, the PCI bus driver will choose to call this function\r
 \r
   For example, if an upstream PPB doesn't support,\r
   prefetchable memory decoding, the PCI bus driver will choose to call this function\r

-  to merge prefectchable memory resource list into normal memory list.\r
+  to merge prefetchable memory resource list into normal memory list.\r

 \r
   If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
   type.\r
 \r
   If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
   type.\r


@@ -152,14 +145,13 @@ InsertResourceNode (
 **/\r
 VOID\r
 MergeResourceTree (\r
 **/\r
 VOID\r
 MergeResourceTree (\r

-  IN PCI_RESOURCE_NODE   *Dst,\r
-  IN PCI_RESOURCE_NODE   *Res,\r
-  IN BOOLEAN             TypeMerge\r
+  IN PCI_RESOURCE_NODE  *Dst,\r
+  IN PCI_RESOURCE_NODE  *Res,\r
+  IN BOOLEAN            TypeMerge\r

   )\r
 {\r
   )\r
 {\r

-\r
-  LIST_ENTRY        *CurrentLink;\r
-  PCI_RESOURCE_NODE *Temp;\r
+  LIST_ENTRY         *CurrentLink;\r
+  PCI_RESOURCE_NODE  *Temp;\r

 \r
   ASSERT (Dst != NULL);\r
   ASSERT (Res != NULL);\r
 \r
   ASSERT (Dst != NULL);\r
   ASSERT (Res != NULL);\r


@@ -167,7 +159,7 @@ MergeResourceTree (
   while (!IsListEmpty (&Res->ChildList)) {\r
     CurrentLink = Res->ChildList.ForwardLink;\r
 \r
   while (!IsListEmpty (&Res->ChildList)) {\r
     CurrentLink = Res->ChildList.ForwardLink;\r
 \r

-    Temp        = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
+    Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r

 \r
     if (TypeMerge) {\r
       Temp->ResType = Dst->ResType;\r
 \r
     if (TypeMerge) {\r
       Temp->ResType = Dst->ResType;\r


@@ -187,22 +179,22 @@ MergeResourceTree (
 **/\r
 VOID\r
 CalculateApertureIo16 (\r
 **/\r
 VOID\r
 CalculateApertureIo16 (\r

-  IN PCI_RESOURCE_NODE    *Bridge\r
+  IN PCI_RESOURCE_NODE  *Bridge\r

   )\r
 {\r
   )\r
 {\r

-  EFI_STATUS              Status;\r
-  UINT64                  Aperture;\r
-  LIST_ENTRY              *CurrentLink;\r
-  PCI_RESOURCE_NODE       *Node;\r
-  UINT64                  Offset;\r
-  EFI_PCI_PLATFORM_POLICY PciPolicy;\r
-  UINT64                  PaddingAperture;\r
+  EFI_STATUS               Status;\r
+  UINT64                   Aperture;\r
+  LIST_ENTRY               *CurrentLink;\r
+  PCI_RESOURCE_NODE        *Node;\r
+  UINT64                   Offset;\r
+  EFI_PCI_PLATFORM_POLICY  PciPolicy;\r
+  UINT64                   PaddingAperture;\r

 \r
   if (!mPolicyDetermined) {\r
     //\r
     // Check PciPlatform policy\r
     //\r
 \r
   if (!mPolicyDetermined) {\r
     //\r
     // Check PciPlatform policy\r
     //\r

-    Status = EFI_NOT_FOUND;\r
+    Status    = EFI_NOT_FOUND;\r

     PciPolicy = 0;\r
     if (gPciPlatformProtocol != NULL) {\r
       Status = gPciPlatformProtocol->GetPlatformPolicy (\r
     PciPolicy = 0;\r
     if (gPciPlatformProtocol != NULL) {\r
       Status = gPciPlatformProtocol->GetPlatformPolicy (\r


@@ -211,7 +203,7 @@ CalculateApertureIo16 (
                                        );\r
     }\r
 \r
                                        );\r
     }\r
 \r

-    if (EFI_ERROR (Status) && gPciOverrideProtocol != NULL) {\r
+    if (EFI_ERROR (Status) && (gPciOverrideProtocol != NULL)) {\r

       Status = gPciOverrideProtocol->GetPlatformPolicy (\r
                                        gPciOverrideProtocol,\r
                                        &PciPolicy\r
       Status = gPciOverrideProtocol->GetPlatformPolicy (\r
                                        gPciOverrideProtocol,\r
                                        &PciPolicy\r


@@ -222,10 +214,12 @@ CalculateApertureIo16 (
       if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
         mReserveIsaAliases = TRUE;\r
       }\r
       if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
         mReserveIsaAliases = TRUE;\r
       }\r

+\r

       if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
         mReserveVgaAliases = TRUE;\r
       }\r
     }\r
       if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
         mReserveVgaAliases = TRUE;\r
       }\r
     }\r

+\r

     mPolicyDetermined = TRUE;\r
   }\r
 \r
     mPolicyDetermined = TRUE;\r
   }\r
 \r


@@ -233,32 +227,31 @@ CalculateApertureIo16 (
   PaddingAperture = 0;\r
 \r
   if (Bridge == NULL) {\r
   PaddingAperture = 0;\r
 \r
   if (Bridge == NULL) {\r

-    return ;\r
+    return;\r

   }\r
 \r
   //\r
   // Assume the bridge is aligned\r
   //\r
   for ( CurrentLink = GetFirstNode (&Bridge->ChildList)\r
   }\r
 \r
   //\r
   // Assume the bridge is aligned\r
   //\r
   for ( CurrentLink = GetFirstNode (&Bridge->ChildList)\r

-      ; !IsNull (&Bridge->ChildList, CurrentLink)\r
-      ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)\r
-      ) {\r
-\r
+        ; !IsNull (&Bridge->ChildList, CurrentLink)\r
+        ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)\r
+        )\r
+  {\r

     Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
     if (Node->ResourceUsage == PciResUsagePadding) {\r
       ASSERT (PaddingAperture == 0);\r
       PaddingAperture = Node->Length;\r
       continue;\r
     }\r
     Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
     if (Node->ResourceUsage == PciResUsagePadding) {\r
       ASSERT (PaddingAperture == 0);\r
       PaddingAperture = Node->Length;\r
       continue;\r
     }\r

+\r

     //\r
     // Consider the aperture alignment\r
     //\r
     Offset = Aperture & (Node->Alignment);\r
 \r
     if (Offset != 0) {\r
     //\r
     // Consider the aperture alignment\r
     //\r
     Offset = Aperture & (Node->Alignment);\r
 \r
     if (Offset != 0) {\r

-\r

       Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
       Aperture = Aperture + (Node->Alignment + 1) - Offset;\r

-\r

     }\r
 \r
     //\r
     }\r
 \r
     //\r


@@ -335,26 +328,25 @@ CalculateApertureIo16 (
   This function is used to calculate the resource aperture\r
   for a given bridge device.\r
 \r
   This function is used to calculate the resource aperture\r
   for a given bridge device.\r
 \r

-  @param Bridge      PCI resouce node for given bridge device.\r
+  @param Bridge      PCI resource node for given bridge device.\r

 \r
 **/\r
 VOID\r
 CalculateResourceAperture (\r
 \r
 **/\r
 VOID\r
 CalculateResourceAperture (\r

-  IN PCI_RESOURCE_NODE    *Bridge\r
+  IN PCI_RESOURCE_NODE  *Bridge\r

   )\r
 {\r
   )\r
 {\r

-  UINT64            Aperture[2];\r
-  LIST_ENTRY        *CurrentLink;\r
-  PCI_RESOURCE_NODE *Node;\r
+  UINT64             Aperture[2];\r
+  LIST_ENTRY         *CurrentLink;\r
+  PCI_RESOURCE_NODE  *Node;\r

 \r
   if (Bridge == NULL) {\r
 \r
   if (Bridge == NULL) {\r

-    return ;\r
+    return;\r

   }\r
 \r
   if (Bridge->ResType == PciBarTypeIo16) {\r
   }\r
 \r
   if (Bridge->ResType == PciBarTypeIo16) {\r

-\r

     CalculateApertureIo16 (Bridge);\r
     CalculateApertureIo16 (Bridge);\r

-    return ;\r
+    return;\r

   }\r
 \r
   Aperture[PciResUsageTypical] = 0;\r
   }\r
 \r
   Aperture[PciResUsageTypical] = 0;\r


@@ -363,17 +355,20 @@ CalculateResourceAperture (
   // Assume the bridge is aligned\r
   //\r
   for ( CurrentLink = GetFirstNode (&Bridge->ChildList)\r
   // Assume the bridge is aligned\r
   //\r
   for ( CurrentLink = GetFirstNode (&Bridge->ChildList)\r

-      ; !IsNull (&Bridge->ChildList, CurrentLink)\r
-      ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)\r
-      ) {\r
+        ; !IsNull (&Bridge->ChildList, CurrentLink)\r
+        ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)\r
+        )\r
+  {\r

     Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
 \r
     //\r
     // It's possible for a bridge to contain multiple padding resource\r
     // nodes due to DegradeResource().\r
     //\r
     Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
 \r
     //\r
     // It's possible for a bridge to contain multiple padding resource\r
     // nodes due to DegradeResource().\r
     //\r

-    ASSERT ((Node->ResourceUsage == PciResUsageTypical) ||\r
-            (Node->ResourceUsage == PciResUsagePadding));\r
+    ASSERT (\r
+      (Node->ResourceUsage == PciResUsageTypical) ||\r
+      (Node->ResourceUsage == PciResUsagePadding)\r
+      );\r

     ASSERT (Node->ResourceUsage < ARRAY_SIZE (Aperture));\r
     //\r
     // Recode current aperture as a offset\r
     ASSERT (Node->ResourceUsage < ARRAY_SIZE (Aperture));\r
     //\r
     // Recode current aperture as a offset\r


@@ -413,7 +408,7 @@ CalculateResourceAperture (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Get IO/Memory resource infor for given PCI device.\r
+  Get IO/Memory resource info for given PCI device.\r

 \r
   @param PciDev     Pci device instance.\r
   @param IoNode     Resource info node for IO .\r
 \r
   @param PciDev     Pci device instance.\r
   @param IoNode     Resource info node for IO .\r


@@ -425,125 +420,123 @@ CalculateResourceAperture (
 **/\r
 VOID\r
 GetResourceFromDevice (\r
 **/\r
 VOID\r
 GetResourceFromDevice (\r

-  IN     PCI_IO_DEVICE     *PciDev,\r
-  IN OUT PCI_RESOURCE_NODE *IoNode,\r
-  IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
-  IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
-  IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
-  IN OUT PCI_RESOURCE_NODE *PMem64Node\r
+  IN     PCI_IO_DEVICE      *PciDev,\r
+  IN OUT PCI_RESOURCE_NODE  *IoNode,\r
+  IN OUT PCI_RESOURCE_NODE  *Mem32Node,\r
+  IN OUT PCI_RESOURCE_NODE  *PMem32Node,\r
+  IN OUT PCI_RESOURCE_NODE  *Mem64Node,\r
+  IN OUT PCI_RESOURCE_NODE  *PMem64Node\r

   )\r
 {\r
   )\r
 {\r

-\r
-  UINT8             Index;\r
-  PCI_RESOURCE_NODE *Node;\r
-  BOOLEAN           ResourceRequested;\r
+  UINT8              Index;\r
+  PCI_RESOURCE_NODE  *Node;\r
+  BOOLEAN            ResourceRequested;\r

 \r
   Node              = NULL;\r
   ResourceRequested = FALSE;\r
 \r
   for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r
 \r
   Node              = NULL;\r
   ResourceRequested = FALSE;\r
 \r
   for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r

-\r

     switch ((PciDev->PciBar)[Index].BarType) {\r
     switch ((PciDev->PciBar)[Index].BarType) {\r

+      case PciBarTypeMem32:\r
+      case PciBarTypeOpRom:\r

 \r
 \r

-    case PciBarTypeMem32:\r
-\r
-      Node = CreateResourceNode (\r
-              PciDev,\r
-              (PciDev->PciBar)[Index].Length,\r
-              (PciDev->PciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypeMem32,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateResourceNode (\r
+                 PciDev,\r
+                 (PciDev->PciBar)[Index].Length,\r
+                 (PciDev->PciBar)[Index].Alignment,\r
+                 Index,\r
+                 (PciDev->PciBar)[Index].BarType,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        Mem32Node,\r
-        Node\r
-        );\r
+        InsertResourceNode (\r
+          Mem32Node,\r
+          Node\r
+          );\r

 \r
 \r

-      ResourceRequested = TRUE;\r
-      break;\r
+        ResourceRequested = TRUE;\r
+        break;\r

 \r
 \r

-    case PciBarTypeMem64:\r
+      case PciBarTypeMem64:\r

 \r
 \r

-      Node = CreateResourceNode (\r
-              PciDev,\r
-              (PciDev->PciBar)[Index].Length,\r
-              (PciDev->PciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypeMem64,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateResourceNode (\r
+                 PciDev,\r
+                 (PciDev->PciBar)[Index].Length,\r
+                 (PciDev->PciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypeMem64,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        Mem64Node,\r
-        Node\r
-        );\r
+        InsertResourceNode (\r
+          Mem64Node,\r
+          Node\r
+          );\r

 \r
 \r

-      ResourceRequested = TRUE;\r
-      break;\r
+        ResourceRequested = TRUE;\r
+        break;\r

 \r
 \r

-    case PciBarTypePMem64:\r
+      case PciBarTypePMem64:\r

 \r
 \r

-      Node = CreateResourceNode (\r
-              PciDev,\r
-              (PciDev->PciBar)[Index].Length,\r
-              (PciDev->PciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypePMem64,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateResourceNode (\r
+                 PciDev,\r
+                 (PciDev->PciBar)[Index].Length,\r
+                 (PciDev->PciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypePMem64,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        PMem64Node,\r
-        Node\r
-        );\r
+        InsertResourceNode (\r
+          PMem64Node,\r
+          Node\r
+          );\r

 \r
 \r

-      ResourceRequested = TRUE;\r
-      break;\r
+        ResourceRequested = TRUE;\r
+        break;\r

 \r
 \r

-    case PciBarTypePMem32:\r
+      case PciBarTypePMem32:\r

 \r
 \r

-      Node = CreateResourceNode (\r
-              PciDev,\r
-              (PciDev->PciBar)[Index].Length,\r
-              (PciDev->PciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypePMem32,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateResourceNode (\r
+                 PciDev,\r
+                 (PciDev->PciBar)[Index].Length,\r
+                 (PciDev->PciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypePMem32,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        PMem32Node,\r
-        Node\r
-        );\r
-      ResourceRequested = TRUE;\r
-      break;\r
+        InsertResourceNode (\r
+          PMem32Node,\r
+          Node\r
+          );\r
+        ResourceRequested = TRUE;\r
+        break;\r

 \r
 \r

-    case PciBarTypeIo16:\r
-    case PciBarTypeIo32:\r
+      case PciBarTypeIo16:\r
+      case PciBarTypeIo32:\r

 \r
 \r

-      Node = CreateResourceNode (\r
-              PciDev,\r
-              (PciDev->PciBar)[Index].Length,\r
-              (PciDev->PciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypeIo16,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateResourceNode (\r
+                 PciDev,\r
+                 (PciDev->PciBar)[Index].Length,\r
+                 (PciDev->PciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypeIo16,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        IoNode,\r
-        Node\r
-        );\r
-      ResourceRequested = TRUE;\r
-      break;\r
+        InsertResourceNode (\r
+          IoNode,\r
+          Node\r
+          );\r
+        ResourceRequested = TRUE;\r
+        break;\r

 \r
 \r

-    case PciBarTypeUnknown:\r
-      break;\r
+      case PciBarTypeUnknown:\r
+        break;\r

 \r
 \r

-    default:\r
-      break;\r
+      default:\r
+        break;\r

     }\r
   }\r
 \r
     }\r
   }\r
 \r


@@ -551,91 +544,90 @@ GetResourceFromDevice (
   // Add VF resource\r
   //\r
   for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r
   // Add VF resource\r
   //\r
   for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r

-\r

     switch ((PciDev->VfPciBar)[Index].BarType) {\r
     switch ((PciDev->VfPciBar)[Index].BarType) {\r

+      case PciBarTypeMem32:\r

 \r
 \r

-    case PciBarTypeMem32:\r
-\r
-      Node = CreateVfResourceNode (\r
-              PciDev,\r
-              (PciDev->VfPciBar)[Index].Length,\r
-              (PciDev->VfPciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypeMem32,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateVfResourceNode (\r
+                 PciDev,\r
+                 (PciDev->VfPciBar)[Index].Length,\r
+                 (PciDev->VfPciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypeMem32,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        Mem32Node,\r
-        Node\r
-        );\r
+        InsertResourceNode (\r
+          Mem32Node,\r
+          Node\r
+          );\r

 \r
 \r

-      break;\r
+        break;\r

 \r
 \r

-    case PciBarTypeMem64:\r
+      case PciBarTypeMem64:\r

 \r
 \r

-      Node = CreateVfResourceNode (\r
-              PciDev,\r
-              (PciDev->VfPciBar)[Index].Length,\r
-              (PciDev->VfPciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypeMem64,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateVfResourceNode (\r
+                 PciDev,\r
+                 (PciDev->VfPciBar)[Index].Length,\r
+                 (PciDev->VfPciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypeMem64,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        Mem64Node,\r
-        Node\r
-        );\r
+        InsertResourceNode (\r
+          Mem64Node,\r
+          Node\r
+          );\r

 \r
 \r

-      break;\r
+        break;\r

 \r
 \r

-    case PciBarTypePMem64:\r
+      case PciBarTypePMem64:\r

 \r
 \r

-      Node = CreateVfResourceNode (\r
-              PciDev,\r
-              (PciDev->VfPciBar)[Index].Length,\r
-              (PciDev->VfPciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypePMem64,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateVfResourceNode (\r
+                 PciDev,\r
+                 (PciDev->VfPciBar)[Index].Length,\r
+                 (PciDev->VfPciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypePMem64,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        PMem64Node,\r
-        Node\r
-        );\r
+        InsertResourceNode (\r
+          PMem64Node,\r
+          Node\r
+          );\r

 \r
 \r

-      break;\r
+        break;\r

 \r
 \r

-    case PciBarTypePMem32:\r
+      case PciBarTypePMem32:\r

 \r
 \r

-      Node = CreateVfResourceNode (\r
-              PciDev,\r
-              (PciDev->VfPciBar)[Index].Length,\r
-              (PciDev->VfPciBar)[Index].Alignment,\r
-              Index,\r
-              PciBarTypePMem32,\r
-              PciResUsageTypical\r
-              );\r
+        Node = CreateVfResourceNode (\r
+                 PciDev,\r
+                 (PciDev->VfPciBar)[Index].Length,\r
+                 (PciDev->VfPciBar)[Index].Alignment,\r
+                 Index,\r
+                 PciBarTypePMem32,\r
+                 PciResUsageTypical\r
+                 );\r

 \r
 \r

-      InsertResourceNode (\r
-        PMem32Node,\r
-        Node\r
-        );\r
-      break;\r
+        InsertResourceNode (\r
+          PMem32Node,\r
+          Node\r
+          );\r
+        break;\r

 \r
 \r

-    case PciBarTypeIo16:\r
-    case PciBarTypeIo32:\r
-      break;\r
+      case PciBarTypeIo16:\r
+      case PciBarTypeIo32:\r
+        break;\r

 \r
 \r

-    case PciBarTypeUnknown:\r
-      break;\r
+      case PciBarTypeUnknown:\r
+        break;\r

 \r
 \r

-    default:\r
-      break;\r
+      default:\r
+        break;\r

     }\r
   }\r
     }\r
   }\r

+\r

   // If there is no resource requested from this device,\r
   // then we indicate this device has been allocated naturally.\r
   //\r
   // If there is no resource requested from this device,\r
   // then we indicate this device has been allocated naturally.\r
   //\r


@@ -660,19 +652,19 @@ GetResourceFromDevice (
 **/\r
 PCI_RESOURCE_NODE *\r
 CreateResourceNode (\r
 **/\r
 PCI_RESOURCE_NODE *\r
 CreateResourceNode (\r

-  IN PCI_IO_DEVICE         *PciDev,\r
-  IN UINT64                Length,\r
-  IN UINT64                Alignment,\r
-  IN UINT8                 Bar,\r
-  IN PCI_BAR_TYPE          ResType,\r
-  IN PCI_RESOURCE_USAGE    ResUsage\r
+  IN PCI_IO_DEVICE       *PciDev,\r
+  IN UINT64              Length,\r
+  IN UINT64              Alignment,\r
+  IN UINT8               Bar,\r
+  IN PCI_BAR_TYPE        ResType,\r
+  IN PCI_RESOURCE_USAGE  ResUsage\r

   )\r
 {\r
   )\r
 {\r

-  PCI_RESOURCE_NODE *Node;\r
+  PCI_RESOURCE_NODE  *Node;\r

 \r
 \r

-  Node    = NULL;\r
+  Node = NULL;\r

 \r
 \r

-  Node    = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));\r
+  Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));\r

   ASSERT (Node != NULL);\r
   if (Node == NULL) {\r
     return NULL;\r
   ASSERT (Node != NULL);\r
   if (Node == NULL) {\r
     return NULL;\r


@@ -707,15 +699,15 @@ CreateResourceNode (
 **/\r
 PCI_RESOURCE_NODE *\r
 CreateVfResourceNode (\r
 **/\r
 PCI_RESOURCE_NODE *\r
 CreateVfResourceNode (\r

-  IN PCI_IO_DEVICE         *PciDev,\r
-  IN UINT64                Length,\r
-  IN UINT64                Alignment,\r
-  IN UINT8                 Bar,\r
-  IN PCI_BAR_TYPE          ResType,\r
-  IN PCI_RESOURCE_USAGE    ResUsage\r
+  IN PCI_IO_DEVICE       *PciDev,\r
+  IN UINT64              Length,\r
+  IN UINT64              Alignment,\r
+  IN UINT8               Bar,\r
+  IN PCI_BAR_TYPE        ResType,\r
+  IN PCI_RESOURCE_USAGE  ResUsage\r

   )\r
 {\r
   )\r
 {\r

-  PCI_RESOURCE_NODE *Node;\r
+  PCI_RESOURCE_NODE  *Node;\r

 \r
   Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);\r
   if (Node == NULL) {\r
 \r
   Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);\r
   if (Node == NULL) {\r


@@ -741,26 +733,25 @@ CreateVfResourceNode (
 **/\r
 VOID\r
 CreateResourceMap (\r
 **/\r
 VOID\r
 CreateResourceMap (\r

-  IN     PCI_IO_DEVICE     *Bridge,\r
-  IN OUT PCI_RESOURCE_NODE *IoNode,\r
-  IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
-  IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
-  IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
-  IN OUT PCI_RESOURCE_NODE *PMem64Node\r
+  IN     PCI_IO_DEVICE      *Bridge,\r
+  IN OUT PCI_RESOURCE_NODE  *IoNode,\r
+  IN OUT PCI_RESOURCE_NODE  *Mem32Node,\r
+  IN OUT PCI_RESOURCE_NODE  *PMem32Node,\r
+  IN OUT PCI_RESOURCE_NODE  *Mem64Node,\r
+  IN OUT PCI_RESOURCE_NODE  *PMem64Node\r

   )\r
 {\r
   )\r
 {\r

-  PCI_IO_DEVICE     *Temp;\r
-  PCI_RESOURCE_NODE *IoBridge;\r
-  PCI_RESOURCE_NODE *Mem32Bridge;\r
-  PCI_RESOURCE_NODE *PMem32Bridge;\r
-  PCI_RESOURCE_NODE *Mem64Bridge;\r
-  PCI_RESOURCE_NODE *PMem64Bridge;\r
-  LIST_ENTRY        *CurrentLink;\r
+  PCI_IO_DEVICE      *Temp;\r
+  PCI_RESOURCE_NODE  *IoBridge;\r
+  PCI_RESOURCE_NODE  *Mem32Bridge;\r
+  PCI_RESOURCE_NODE  *PMem32Bridge;\r
+  PCI_RESOURCE_NODE  *Mem64Bridge;\r
+  PCI_RESOURCE_NODE  *PMem64Bridge;\r
+  LIST_ENTRY         *CurrentLink;\r

 \r
   CurrentLink = Bridge->ChildList.ForwardLink;\r
 \r
   while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
 \r
   CurrentLink = Bridge->ChildList.ForwardLink;\r
 \r
   while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r

-\r

     Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
 \r
     //\r
     Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
 \r
     //\r


@@ -779,7 +770,6 @@ CreateResourceMap (
       );\r
 \r
     if (IS_PCI_BRIDGE (&Temp->Pci)) {\r
       );\r
 \r
     if (IS_PCI_BRIDGE (&Temp->Pci)) {\r

-\r

       //\r
       // If the device has children, create a bridge resource node for this PPB\r
       // Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r
       //\r
       // If the device has children, create a bridge resource node for this PPB\r
       // Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r


@@ -831,7 +821,7 @@ CreateResourceMap (
                        );\r
 \r
       //\r
                        );\r
 \r
       //\r

-      // Recursively create resouce map on this bridge\r
+      // Recursively create resource map on this bridge\r

       //\r
       CreateResourceMap (\r
         Temp,\r
       //\r
       CreateResourceMap (\r
         Temp,\r


@@ -915,7 +905,6 @@ CreateResourceMap (
         FreePool (PMem64Bridge);\r
         PMem64Bridge = NULL;\r
       }\r
         FreePool (PMem64Bridge);\r
         PMem64Bridge = NULL;\r
       }\r

-\r

     }\r
 \r
     //\r
     }\r
 \r
     //\r


@@ -981,12 +970,12 @@ CreateResourceMap (
 **/\r
 VOID\r
 ResourcePaddingPolicy (\r
 **/\r
 VOID\r
 ResourcePaddingPolicy (\r

-  IN PCI_IO_DEVICE     *PciDev,\r
-  IN PCI_RESOURCE_NODE *IoNode,\r
-  IN PCI_RESOURCE_NODE *Mem32Node,\r
-  IN PCI_RESOURCE_NODE *PMem32Node,\r
-  IN PCI_RESOURCE_NODE *Mem64Node,\r
-  IN PCI_RESOURCE_NODE *PMem64Node\r
+  IN PCI_IO_DEVICE      *PciDev,\r
+  IN PCI_RESOURCE_NODE  *IoNode,\r
+  IN PCI_RESOURCE_NODE  *Mem32Node,\r
+  IN PCI_RESOURCE_NODE  *PMem32Node,\r
+  IN PCI_RESOURCE_NODE  *Mem64Node,\r
+  IN PCI_RESOURCE_NODE  *PMem64Node\r

   )\r
 {\r
   //\r
   )\r
 {\r
   //\r


@@ -1020,18 +1009,18 @@ ResourcePaddingPolicy (
 **/\r
 VOID\r
 DegradeResource (\r
 **/\r
 VOID\r
 DegradeResource (\r

-  IN PCI_IO_DEVICE     *Bridge,\r
-  IN PCI_RESOURCE_NODE *Mem32Node,\r
-  IN PCI_RESOURCE_NODE *PMem32Node,\r
-  IN PCI_RESOURCE_NODE *Mem64Node,\r
-  IN PCI_RESOURCE_NODE *PMem64Node\r
+  IN PCI_IO_DEVICE      *Bridge,\r
+  IN PCI_RESOURCE_NODE  *Mem32Node,\r
+  IN PCI_RESOURCE_NODE  *PMem32Node,\r
+  IN PCI_RESOURCE_NODE  *Mem64Node,\r
+  IN PCI_RESOURCE_NODE  *PMem64Node\r

   )\r
 {\r
   )\r
 {\r

-  PCI_IO_DEVICE        *PciIoDevice;\r
-  LIST_ENTRY           *ChildDeviceLink;\r
-  LIST_ENTRY           *ChildNodeLink;\r
-  LIST_ENTRY           *NextChildNodeLink;\r
-  PCI_RESOURCE_NODE    *ResourceNode;\r
+  PCI_IO_DEVICE      *PciIoDevice;\r
+  LIST_ENTRY         *ChildDeviceLink;\r
+  LIST_ENTRY         *ChildNodeLink;\r
+  LIST_ENTRY         *NextChildNodeLink;\r
+  PCI_RESOURCE_NODE  *ResourceNode;\r

 \r
   if (FeaturePcdGet (PcdPciDegradeResourceForOptionRom)) {\r
     //\r
 \r
   if (FeaturePcdGet (PcdPciDegradeResourceForOptionRom)) {\r
     //\r


@@ -1045,15 +1034,17 @@ DegradeResource (
         if (!IsListEmpty (&Mem64Node->ChildList)) {\r
           ChildNodeLink = Mem64Node->ChildList.ForwardLink;\r
           while (ChildNodeLink != &Mem64Node->ChildList) {\r
         if (!IsListEmpty (&Mem64Node->ChildList)) {\r
           ChildNodeLink = Mem64Node->ChildList.ForwardLink;\r
           while (ChildNodeLink != &Mem64Node->ChildList) {\r

-            ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);\r
+            ResourceNode      = RESOURCE_NODE_FROM_LINK (ChildNodeLink);\r

             NextChildNodeLink = ChildNodeLink->ForwardLink;\r
 \r
             if ((ResourceNode->PciDev == PciIoDevice) &&\r
                 (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)\r
             NextChildNodeLink = ChildNodeLink->ForwardLink;\r
 \r
             if ((ResourceNode->PciDev == PciIoDevice) &&\r
                 (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)\r

-                ) {\r
+                )\r
+            {\r

               RemoveEntryList (ChildNodeLink);\r
               InsertResourceNode (Mem32Node, ResourceNode);\r
             }\r
               RemoveEntryList (ChildNodeLink);\r
               InsertResourceNode (Mem32Node, ResourceNode);\r
             }\r

+\r

             ChildNodeLink = NextChildNodeLink;\r
           }\r
         }\r
             ChildNodeLink = NextChildNodeLink;\r
           }\r
         }\r


@@ -1061,20 +1052,22 @@ DegradeResource (
         if (!IsListEmpty (&PMem64Node->ChildList)) {\r
           ChildNodeLink = PMem64Node->ChildList.ForwardLink;\r
           while (ChildNodeLink != &PMem64Node->ChildList) {\r
         if (!IsListEmpty (&PMem64Node->ChildList)) {\r
           ChildNodeLink = PMem64Node->ChildList.ForwardLink;\r
           while (ChildNodeLink != &PMem64Node->ChildList) {\r

-            ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);\r
+            ResourceNode      = RESOURCE_NODE_FROM_LINK (ChildNodeLink);\r

             NextChildNodeLink = ChildNodeLink->ForwardLink;\r
 \r
             if ((ResourceNode->PciDev == PciIoDevice) &&\r
                 (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)\r
             NextChildNodeLink = ChildNodeLink->ForwardLink;\r
 \r
             if ((ResourceNode->PciDev == PciIoDevice) &&\r
                 (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)\r

-                ) {\r
+                )\r
+            {\r

               RemoveEntryList (ChildNodeLink);\r
               InsertResourceNode (PMem32Node, ResourceNode);\r
             }\r
               RemoveEntryList (ChildNodeLink);\r
               InsertResourceNode (PMem32Node, ResourceNode);\r
             }\r

+\r

             ChildNodeLink = NextChildNodeLink;\r
           }\r
         }\r
             ChildNodeLink = NextChildNodeLink;\r
           }\r
         }\r

-\r

       }\r
       }\r

+\r

       ChildDeviceLink = ChildDeviceLink->ForwardLink;\r
     }\r
   }\r
       ChildDeviceLink = ChildDeviceLink->ForwardLink;\r
     }\r
   }\r


@@ -1100,11 +1093,11 @@ DegradeResource (
     // if the bridge does not support MEM64, degrade MEM64 to MEM32\r
     //\r
     if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_MEM64_DECODE_SUPPORTED)) {\r
     // if the bridge does not support MEM64, degrade MEM64 to MEM32\r
     //\r
     if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_MEM64_DECODE_SUPPORTED)) {\r

-        MergeResourceTree (\r
-          Mem32Node,\r
-          Mem64Node,\r
-          TRUE\r
-          );\r
+      MergeResourceTree (\r
+        Mem32Node,\r
+        Mem64Node,\r
+        TRUE\r
+        );\r

     }\r
 \r
     //\r
     }\r
 \r
     //\r


@@ -1116,13 +1109,13 @@ DegradeResource (
         PMem64Node,\r
         TRUE\r
         );\r
         PMem64Node,\r
         TRUE\r
         );\r

-    } \r
+    }\r

 \r
     //\r
     // if both PMEM64 and PMEM32 requests from child devices, which can not be satisfied\r
     // by a P2P bridge simultaneously, keep PMEM64 and degrade PMEM32 to MEM32.\r
     //\r
 \r
     //\r
     // if both PMEM64 and PMEM32 requests from child devices, which can not be satisfied\r
     // by a P2P bridge simultaneously, keep PMEM64 and degrade PMEM32 to MEM32.\r
     //\r

-    if (!IsListEmpty (&PMem64Node->ChildList) && Bridge->Parent != NULL) {\r
+    if (!IsListEmpty (&PMem64Node->ChildList) && (Bridge->Parent != NULL)) {\r

       MergeResourceTree (\r
         Mem32Node,\r
         PMem32Node,\r
       MergeResourceTree (\r
         Mem32Node,\r
         PMem32Node,\r


@@ -1179,8 +1172,8 @@ DegradeResource (
 **/\r
 BOOLEAN\r
 BridgeSupportResourceDecode (\r
 **/\r
 BOOLEAN\r
 BridgeSupportResourceDecode (\r

-  IN PCI_IO_DEVICE *Bridge,\r
-  IN UINT32        Decode\r
+  IN PCI_IO_DEVICE  *Bridge,\r
+  IN UINT32         Decode\r

   )\r
 {\r
   if (((Bridge->Decodes) & Decode) != 0) {\r
   )\r
 {\r
   if (((Bridge->Decodes) & Decode) != 0) {\r


@@ -1194,23 +1187,23 @@ BridgeSupportResourceDecode (
   This function is used to program the resource allocated\r
   for each resource node under specified bridge.\r
 \r
   This function is used to program the resource allocated\r
   for each resource node under specified bridge.\r
 \r

-  @param Base     Base address of resource to be progammed.\r
+  @param Base     Base address of resource to be programmed.\r

   @param Bridge   PCI resource node for the bridge device.\r
 \r
   @param Bridge   PCI resource node for the bridge device.\r
 \r

-  @retval EFI_SUCCESS            Successfully to program all resouces\r
+  @retval EFI_SUCCESS            Successfully to program all resources\r

                                  on given PCI bridge device.\r
   @retval EFI_OUT_OF_RESOURCES   Base is all one.\r
 \r
 **/\r
 EFI_STATUS\r
 ProgramResource (\r
                                  on given PCI bridge device.\r
   @retval EFI_OUT_OF_RESOURCES   Base is all one.\r
 \r
 **/\r
 EFI_STATUS\r
 ProgramResource (\r

-  IN UINT64            Base,\r
-  IN PCI_RESOURCE_NODE *Bridge\r
+  IN UINT64             Base,\r
+  IN PCI_RESOURCE_NODE  *Bridge\r

   )\r
 {\r
   )\r
 {\r

-  LIST_ENTRY        *CurrentLink;\r
-  PCI_RESOURCE_NODE *Node;\r
-  EFI_STATUS        Status;\r
+  LIST_ENTRY         *CurrentLink;\r
+  PCI_RESOURCE_NODE  *Node;\r
+  EFI_STATUS         Status;\r

 \r
   if (Base == gAllOne) {\r
     return EFI_OUT_OF_RESOURCES;\r
 \r
   if (Base == gAllOne) {\r
     return EFI_OUT_OF_RESOURCES;\r


@@ -1219,11 +1212,9 @@ ProgramResource (
   CurrentLink = Bridge->ChildList.ForwardLink;\r
 \r
   while (CurrentLink != &Bridge->ChildList) {\r
   CurrentLink = Bridge->ChildList.ForwardLink;\r
 \r
   while (CurrentLink != &Bridge->ChildList) {\r

-\r

     Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
 \r
     if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {\r
     Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
 \r
     if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {\r

-\r

       if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
         //\r
         // Program the PCI Card Bus device\r
       if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
         //\r
         // Program the PCI Card Bus device\r


@@ -1256,19 +1247,19 @@ ProgramResource (
 /**\r
   Program Bar register for PCI device.\r
 \r
 /**\r
   Program Bar register for PCI device.\r
 \r

-  @param Base  Base address for PCI device resource to be progammed.\r
-  @param Node  Point to resoure node structure.\r
+  @param Base  Base address for PCI device resource to be programmed.\r
+  @param Node  Point to resource node structure.\r

 \r
 **/\r
 VOID\r
 ProgramBar (\r
 \r
 **/\r
 VOID\r
 ProgramBar (\r

-  IN UINT64            Base,\r
-  IN PCI_RESOURCE_NODE *Node\r
+  IN UINT64             Base,\r
+  IN PCI_RESOURCE_NODE  *Node\r

   )\r
 {\r
   )\r
 {\r

-  EFI_PCI_IO_PROTOCOL *PciIo;\r
-  UINT64              Address;\r
-  UINT32              Address32;\r
+  EFI_PCI_IO_PROTOCOL  *PciIo;\r
+  UINT64               Address;\r
+  UINT32               Address32;\r

 \r
   ASSERT (Node->Bar < PCI_MAX_BAR);\r
 \r
 \r
   ASSERT (Node->Bar < PCI_MAX_BAR);\r
 \r


@@ -1294,72 +1285,77 @@ ProgramBar (
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r

+    case PciBarTypeIo16:\r
+    case PciBarTypeIo32:\r
+    case PciBarTypeMem32:\r
+    case PciBarTypePMem32:\r

 \r
 \r

-  case PciBarTypeIo16:\r
-  case PciBarTypeIo32:\r
-  case PciBarTypeMem32:\r
-  case PciBarTypePMem32:\r
-\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
-                 1,\r
-                 &Address\r
-                 );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+                   1,\r
+                   &Address\r
+                   );\r
+    //\r
+    // Continue to the case PciBarTypeOpRom to set the BaseAddress.\r
+    // PciBarTypeOpRom is a virtual BAR only in root bridge, to capture\r
+    // the MEM32 resource requirement for Option ROM shadow.\r
+    //\r

 \r
 \r

-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+    case PciBarTypeOpRom:\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r

 \r
 \r

-    break;\r
+      break;\r

 \r
 \r

-  case PciBarTypeMem64:\r
-  case PciBarTypePMem64:\r
+    case PciBarTypeMem64:\r
+    case PciBarTypePMem64:\r

 \r
 \r

-    Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
+      Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);\r

 \r
 \r

-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) RShiftU64 (Address, 32);\r
+      Address32 = (UINT32)RShiftU64 (Address, 32);\r

 \r
 \r

-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   (UINT8)((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r

 \r
 \r

-    break;\r
+      break;\r

 \r
 \r

-  default:\r
-    break;\r
+    default:\r
+      break;\r

   }\r
 }\r
 \r
 /**\r
   Program IOV VF Bar register for PCI device.\r
 \r
   }\r
 }\r
 \r
 /**\r
   Program IOV VF Bar register for PCI device.\r
 \r

-  @param Base  Base address for PCI device resource to be progammed.\r
-  @param Node  Point to resoure node structure.\r
+  @param Base  Base address for PCI device resource to be programmed.\r
+  @param Node  Point to resource node structure.\r

 \r
 **/\r
 EFI_STATUS\r
 ProgramVfBar (\r
 \r
 **/\r
 EFI_STATUS\r
 ProgramVfBar (\r

-  IN UINT64            Base,\r
-  IN PCI_RESOURCE_NODE *Node\r
+  IN UINT64             Base,\r
+  IN PCI_RESOURCE_NODE  *Node\r

   )\r
 {\r
   )\r
 {\r

-  EFI_PCI_IO_PROTOCOL *PciIo;\r
-  UINT64              Address;\r
-  UINT32              Address32;\r
+  EFI_PCI_IO_PROTOCOL  *PciIo;\r
+  UINT64               Address;\r
+  UINT32               Address32;\r

 \r
   ASSERT (Node->Bar < PCI_MAX_BAR);\r
   ASSERT (Node->Virtual);\r
 \r
   ASSERT (Node->Bar < PCI_MAX_BAR);\r
   ASSERT (Node->Virtual);\r


@@ -1378,85 +1374,84 @@ ProgramVfBar (
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch ((Node->PciDev->VfPciBar[Node->Bar]).BarType) {\r
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch ((Node->PciDev->VfPciBar[Node->Bar]).BarType) {\r

+    case PciBarTypeMem32:\r
+    case PciBarTypePMem32:\r

 \r
 \r

-  case PciBarTypeMem32:\r
-  case PciBarTypePMem32:\r
-\r
-    PciIo->Pci.Write (\r
-                PciIo,\r
-                EfiPciIoWidthUint32,\r
-                (Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
-                1,\r
-                &Address\r
-                );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   (Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
+                   1,\r
+                   &Address\r
+                   );\r

 \r
 \r

-    Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;\r
-    break;\r
+      Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;\r
+      break;\r

 \r
 \r

-  case PciBarTypeMem64:\r
-  case PciBarTypePMem64:\r
+    case PciBarTypeMem64:\r
+    case PciBarTypePMem64:\r

 \r
 \r

-    Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
+      Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);\r

 \r
 \r

-    PciIo->Pci.Write (\r
-                PciIo,\r
-                EfiPciIoWidthUint32,\r
-                (Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
-                1,\r
-                &Address32\r
-                );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   (Node->PciDev->VfPciBar[Node->Bar]).Offset,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) RShiftU64 (Address, 32);\r
+      Address32 = (UINT32)RShiftU64 (Address, 32);\r

 \r
 \r

-    PciIo->Pci.Write (\r
-                PciIo,\r
-                EfiPciIoWidthUint32,\r
-                ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),\r
-                1,\r
-                &Address32\r
-                );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;\r
-    break;\r
+      Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;\r
+      break;\r

 \r
 \r

-  case PciBarTypeIo16:\r
-  case PciBarTypeIo32:\r
-    break;\r
+    case PciBarTypeIo16:\r
+    case PciBarTypeIo32:\r
+      break;\r

 \r
 \r

-  default:\r
-    break;\r
+    default:\r
+      break;\r

   }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r
 /**\r
   }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r
 /**\r

-  Program PCI-PCI bridge apperture.\r
+  Program PCI-PCI bridge aperture.\r

 \r
   @param Base  Base address for resource.\r
 \r
   @param Base  Base address for resource.\r

-  @param Node  Point to resoure node structure.\r
+  @param Node  Point to resource node structure.\r

 \r
 **/\r
 VOID\r
 ProgramPpbApperture (\r
 \r
 **/\r
 VOID\r
 ProgramPpbApperture (\r

-  IN UINT64            Base,\r
-  IN PCI_RESOURCE_NODE *Node\r
+  IN UINT64             Base,\r
+  IN PCI_RESOURCE_NODE  *Node\r

   )\r
 {\r
   )\r
 {\r

-  EFI_PCI_IO_PROTOCOL *PciIo;\r
-  UINT64              Address;\r
-  UINT32              Address32;\r
+  EFI_PCI_IO_PROTOCOL  *PciIo;\r
+  UINT64               Address;\r
+  UINT32               Address32;\r

 \r
   Address = 0;\r
   //\r
   // If no device resource of this PPB, return anyway\r
 \r
   Address = 0;\r
   //\r
   // If no device resource of this PPB, return anyway\r

-  // Apperture is set default in the initialization code\r
+  // Aperture is set default in the initialization code\r

   //\r
   //\r

-  if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {\r
+  if ((Node->Length == 0) || (Node->ResourceUsage == PciResUsagePadding)) {\r

     //\r
     // For padding resource node, just ignore when programming\r
     //\r
     //\r
     // For padding resource node, just ignore when programming\r
     //\r

-    return ;\r
+    return;\r

   }\r
 \r
   PciIo   = &(Node->PciDev->PciIo);\r
   }\r
 \r
   PciIo   = &(Node->PciDev->PciIo);\r


@@ -1468,219 +1463,239 @@ ProgramPpbApperture (
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch (Node->Bar) {\r
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch (Node->Bar) {\r

+    case PPB_BAR_0:\r
+    case PPB_BAR_1:\r
+      switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r
+        case PciBarTypeIo16:\r
+        case PciBarTypeIo32:\r
+        case PciBarTypeMem32:\r
+        case PciBarTypePMem32:\r
+\r
+          PciIo->Pci.Write (\r
+                       PciIo,\r
+                       EfiPciIoWidthUint32,\r
+                       (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+                       1,\r
+                       &Address\r
+                       );\r

 \r
 \r

-  case PPB_BAR_0:\r
-  case PPB_BAR_1:\r
-    switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r
-\r
-      case PciBarTypeIo16:\r
-      case PciBarTypeIo32:\r
-      case PciBarTypeMem32:\r
-      case PciBarTypePMem32:\r
-\r
-        PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
-                 1,\r
-                 &Address\r
-                 );\r
+          Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+          Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+          break;\r

 \r
 \r

-        Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-        Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-        break;\r
+        case PciBarTypeMem64:\r
+        case PciBarTypePMem64:\r

 \r
 \r

-      case PciBarTypeMem64:\r
-      case PciBarTypePMem64:\r
+          Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);\r

 \r
 \r

-        Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
+          PciIo->Pci.Write (\r
+                       PciIo,\r
+                       EfiPciIoWidthUint32,\r
+                       (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+                       1,\r
+                       &Address32\r
+                       );\r

 \r
 \r

-        PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+          Address32 = (UINT32)RShiftU64 (Address, 32);\r

 \r
 \r

-        Address32 = (UINT32) RShiftU64 (Address, 32);\r
+          PciIo->Pci.Write (\r
+                       PciIo,\r
+                       EfiPciIoWidthUint32,\r
+                       (UINT8)((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
+                       1,\r
+                       &Address32\r
+                       );\r

 \r
 \r

-        PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
-                 1,\r
-                 &Address32\r
-                 );\r
+          Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+          Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+          break;\r

 \r
 \r

-        Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-        Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-        break;\r
+        default:\r
+          break;\r
+      }\r

 \r
 \r

-      default:\r
-        break;\r
-    }\r
-    break;\r
+      break;\r

 \r
 \r

-  case PPB_IO_RANGE:\r
+    case PPB_IO_RANGE:\r

 \r
 \r

-    Address32 = ((UINT32) (Address)) >> 8;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint8,\r
-                 0x1C,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = ((UINT32)(Address)) >> 8;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint8,\r
+                   0x1C,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 >>= 8;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 0x30,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 >>= 8;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   0x30,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) (Address + Node->Length - 1);\r
-    Address32 = ((UINT32) (Address32)) >> 8;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint8,\r
-                 0x1D,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = (UINT32)(Address + Node->Length - 1);\r
+      Address32 = ((UINT32)(Address32)) >> 8;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint8,\r
+                   0x1D,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 >>= 8;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 0x32,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 >>= 8;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   0x32,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    break;\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      break;\r

 \r
 \r

-  case PPB_MEM32_RANGE:\r
+    case PPB_MEM32_RANGE:\r

 \r
 \r

-    Address32 = ((UINT32) (Address)) >> 16;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 0x20,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = ((UINT32)(Address)) >> 16;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   0x20,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) (Address + Node->Length - 1);\r
-    Address32 = ((UINT32) (Address32)) >> 16;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 0x22,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = (UINT32)(Address + Node->Length - 1);\r
+      Address32 = ((UINT32)(Address32)) >> 16;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   0x22,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    break;\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      break;\r

 \r
 \r

-  case PPB_PMEM32_RANGE:\r
-  case PPB_PMEM64_RANGE:\r
+    case PPB_PMEM32_RANGE:\r
+    case PPB_PMEM64_RANGE:\r

 \r
 \r

-    Address32 = ((UINT32) (Address)) >> 16;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 0x24,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = ((UINT32)(Address)) >> 16;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   0x24,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) (Address + Node->Length - 1);\r
-    Address32 = ((UINT32) (Address32)) >> 16;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 0x26,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = (UINT32)(Address + Node->Length - 1);\r
+      Address32 = ((UINT32)(Address32)) >> 16;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   0x26,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) RShiftU64 (Address, 32);\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 0x28,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = (UINT32)RShiftU64 (Address, 32);\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   0x28,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 0x2C,\r
-                 1,\r
-                 &Address32\r
-                 );\r
+      Address32 = (UINT32)RShiftU64 ((Address + Node->Length - 1), 32);\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   0x2C,\r
+                   1,\r
+                   &Address32\r
+                   );\r

 \r
 \r

-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    break;\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      break;\r

 \r
 \r

-  default:\r
-    break;\r
+    default:\r
+      break;\r

   }\r
 }\r
 \r
 /**\r
   Program parent bridge for Option Rom.\r
 \r
   }\r
 }\r
 \r
 /**\r
   Program parent bridge for Option Rom.\r
 \r

-  @param PciDevice      Pci deivce instance.\r
-  @param OptionRomBase  Base address for Optiona Rom.\r
+  @param PciDevice      Pci device instance.\r
+  @param OptionRomBase  Base address for Option Rom.\r

   @param Enable         Enable or disable PCI memory.\r
 \r
 **/\r
 VOID\r
   @param Enable         Enable or disable PCI memory.\r
 \r
 **/\r
 VOID\r

-ProgrameUpstreamBridgeForRom (\r
-  IN PCI_IO_DEVICE   *PciDevice,\r
-  IN UINT32          OptionRomBase,\r
-  IN BOOLEAN         Enable\r
+ProgramUpstreamBridgeForRom (\r
+  IN PCI_IO_DEVICE  *PciDevice,\r
+  IN UINT32         OptionRomBase,\r
+  IN BOOLEAN        Enable\r

   )\r
 {\r
   )\r
 {\r

-  PCI_IO_DEVICE     *Parent;\r
-  PCI_RESOURCE_NODE Node;\r
+  PCI_IO_DEVICE        *Parent;\r
+  EFI_PCI_IO_PROTOCOL  *PciIo;\r
+  UINT16               Base;\r
+  UINT16               Limit;\r
+\r

   //\r
   // For root bridge, just return.\r
   //\r
   Parent = PciDevice->Parent;\r
   //\r
   // For root bridge, just return.\r
   //\r
   Parent = PciDevice->Parent;\r

-  ZeroMem (&Node, sizeof (Node));\r

   while (Parent != NULL) {\r
     if (!IS_PCI_BRIDGE (&Parent->Pci)) {\r
       break;\r
     }\r
 \r
   while (Parent != NULL) {\r
     if (!IS_PCI_BRIDGE (&Parent->Pci)) {\r
       break;\r
     }\r
 \r

-    Node.PciDev     = Parent;\r
-    Node.Length     = PciDevice->RomSize;\r
-    Node.Alignment  = 0;\r
-    Node.Bar        = PPB_MEM32_RANGE;\r
-    Node.ResType    = PciBarTypeMem32;\r
-    Node.Offset     = 0;\r
+    PciIo = &Parent->PciIo;\r

 \r
     //\r
 \r
     //\r

-    // Program PPB to only open a single <= 16MB apperture\r
+    // Program PPB to only open a single <= 16MB aperture\r

     //\r
     if (Enable) {\r
     //\r
     if (Enable) {\r

-      ProgramPpbApperture (OptionRomBase, &Node);\r
+      //\r
+      // Only cover MMIO for Option ROM.\r
+      //\r
+      Base  = (UINT16)(OptionRomBase >> 16);\r
+      Limit = (UINT16)((OptionRomBase + PciDevice->RomSize - 1) >> 16);\r
+      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);\r
+      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), 1, &Limit);\r
+\r

       PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     } else {\r
       PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     } else {\r

-      InitializePpb (Parent);\r
+      //\r
+      // Cover 32bit MMIO for devices below the bridge.\r
+      //\r
+      if (Parent->PciBar[PPB_MEM32_RANGE].Length == 0) {\r
+        //\r
+        // When devices under the bridge contains Option ROM and doesn't require 32bit MMIO.\r
+        //\r
+        Base  = (UINT16)gAllOne;\r
+        Limit = (UINT16)gAllZero;\r
+      } else {\r
+        Base  = (UINT16)((UINT32)Parent->PciBar[PPB_MEM32_RANGE].BaseAddress >> 16);\r
+        Limit = (UINT16)((UINT32)(Parent->PciBar[PPB_MEM32_RANGE].BaseAddress\r
+                                  + Parent->PciBar[PPB_MEM32_RANGE].Length - 1) >> 16);\r
+      }\r
+\r
+      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);\r
+      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), 1, &Limit);\r
+\r

       PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     }\r
 \r
       PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     }\r
 \r


@@ -1699,11 +1714,11 @@ ProgrameUpstreamBridgeForRom (
 **/\r
 BOOLEAN\r
 ResourceRequestExisted (\r
 **/\r
 BOOLEAN\r
 ResourceRequestExisted (\r

-  IN PCI_RESOURCE_NODE    *Bridge\r
+  IN PCI_RESOURCE_NODE  *Bridge\r

   )\r
 {\r
   if (Bridge != NULL) {\r
   )\r
 {\r
   if (Bridge != NULL) {\r

-    if (!IsListEmpty (&Bridge->ChildList) || Bridge->Length != 0) {\r
+    if (!IsListEmpty (&Bridge->ChildList) || (Bridge->Length != 0)) {\r

       return TRUE;\r
     }\r
   }\r
       return TRUE;\r
     }\r
   }\r


@@ -1721,8 +1736,8 @@ ResourceRequestExisted (
 **/\r
 VOID\r
 InitializeResourcePool (\r
 **/\r
 VOID\r
 InitializeResourcePool (\r

-  IN OUT PCI_RESOURCE_NODE   *ResourcePool,\r
-  IN     PCI_BAR_TYPE        ResourceType\r
+  IN OUT PCI_RESOURCE_NODE  *ResourcePool,\r
+  IN     PCI_BAR_TYPE       ResourceType\r

   )\r
 {\r
   ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));\r
   )\r
 {\r
   ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));\r


@@ -1732,24 +1747,23 @@ InitializeResourcePool (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Destory given resource tree.\r
+  Destroy given resource tree.\r

 \r
   @param Bridge  PCI resource root node of resource tree.\r
 \r
 **/\r
 VOID\r
 DestroyResourceTree (\r
 \r
   @param Bridge  PCI resource root node of resource tree.\r
 \r
 **/\r
 VOID\r
 DestroyResourceTree (\r

-  IN PCI_RESOURCE_NODE *Bridge\r
+  IN PCI_RESOURCE_NODE  *Bridge\r

   )\r
 {\r
   )\r
 {\r

-  PCI_RESOURCE_NODE *Temp;\r
-  LIST_ENTRY        *CurrentLink;\r
+  PCI_RESOURCE_NODE  *Temp;\r
+  LIST_ENTRY         *CurrentLink;\r

 \r
   while (!IsListEmpty (&Bridge->ChildList)) {\r
 \r
   while (!IsListEmpty (&Bridge->ChildList)) {\r

-\r

     CurrentLink = Bridge->ChildList.ForwardLink;\r
 \r
     CurrentLink = Bridge->ChildList.ForwardLink;\r
 \r

-    Temp        = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
+    Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r

     ASSERT (Temp);\r
 \r
     RemoveEntryList (CurrentLink);\r
     ASSERT (Temp);\r
 \r
     RemoveEntryList (CurrentLink);\r


@@ -1775,21 +1789,21 @@ DestroyResourceTree (
 **/\r
 VOID\r
 ResourcePaddingForCardBusBridge (\r
 **/\r
 VOID\r
 ResourcePaddingForCardBusBridge (\r

-  IN PCI_IO_DEVICE        *PciDev,\r
-  IN PCI_RESOURCE_NODE    *IoNode,\r
-  IN PCI_RESOURCE_NODE    *Mem32Node,\r
-  IN PCI_RESOURCE_NODE    *PMem32Node,\r
-  IN PCI_RESOURCE_NODE    *Mem64Node,\r
-  IN PCI_RESOURCE_NODE    *PMem64Node\r
+  IN PCI_IO_DEVICE      *PciDev,\r
+  IN PCI_RESOURCE_NODE  *IoNode,\r
+  IN PCI_RESOURCE_NODE  *Mem32Node,\r
+  IN PCI_RESOURCE_NODE  *PMem32Node,\r
+  IN PCI_RESOURCE_NODE  *Mem64Node,\r
+  IN PCI_RESOURCE_NODE  *PMem64Node\r

   )\r
 {\r
   )\r
 {\r

-  PCI_RESOURCE_NODE *Node;\r
+  PCI_RESOURCE_NODE  *Node;\r

 \r
   Node = NULL;\r
 \r
   //\r
   // Memory Base/Limit Register 0\r
 \r
   Node = NULL;\r
 \r
   //\r
   // Memory Base/Limit Register 0\r

-  // Bar 1 denodes memory range 0\r
+  // Bar 1 decodes memory range 0\r

   //\r
   Node = CreateResourceNode (\r
            PciDev,\r
   //\r
   Node = CreateResourceNode (\r
            PciDev,\r


@@ -1807,7 +1821,7 @@ ResourcePaddingForCardBusBridge (
 \r
   //\r
   // Memory Base/Limit Register 1\r
 \r
   //\r
   // Memory Base/Limit Register 1\r

-  // Bar 2 denodes memory range1\r
+  // Bar 2 decodes memory range1\r

   //\r
   Node = CreateResourceNode (\r
            PciDev,\r
   //\r
   Node = CreateResourceNode (\r
            PciDev,\r


@@ -1825,7 +1839,7 @@ ResourcePaddingForCardBusBridge (
 \r
   //\r
   // Io Base/Limit\r
 \r
   //\r
   // Io Base/Limit\r

-  // Bar 3 denodes io range 0\r
+  // Bar 3 decodes io range 0\r

   //\r
   Node = CreateResourceNode (\r
            PciDev,\r
   //\r
   Node = CreateResourceNode (\r
            PciDev,\r


@@ -1843,7 +1857,7 @@ ResourcePaddingForCardBusBridge (
 \r
   //\r
   // Io Base/Limit\r
 \r
   //\r
   // Io Base/Limit\r

-  // Bar 4 denodes io range 0\r
+  // Bar 4 decodes io range 0\r

   //\r
   Node = CreateResourceNode (\r
            PciDev,\r
   //\r
   Node = CreateResourceNode (\r
            PciDev,\r


@@ -1869,14 +1883,14 @@ ResourcePaddingForCardBusBridge (
 **/\r
 VOID\r
 ProgramP2C (\r
 **/\r
 VOID\r
 ProgramP2C (\r

-  IN UINT64            Base,\r
-  IN PCI_RESOURCE_NODE *Node\r
+  IN UINT64             Base,\r
+  IN PCI_RESOURCE_NODE  *Node\r

   )\r
 {\r
   )\r
 {\r

-  EFI_PCI_IO_PROTOCOL *PciIo;\r
-  UINT64              Address;\r
-  UINT64              TempAddress;\r
-  UINT16              BridgeControl;\r
+  EFI_PCI_IO_PROTOCOL  *PciIo;\r
+  UINT64               Address;\r
+  UINT64               TempAddress;\r
+  UINT16               BridgeControl;\r

 \r
   Address = 0;\r
   PciIo   = &(Node->PciDev->PciIo);\r
 \r
   Address = 0;\r
   PciIo   = &(Node->PciDev->PciIo);\r


@@ -1892,205 +1906,200 @@ ProgramP2C (
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch (Node->Bar) {\r
   Node->PciDev->Allocated = TRUE;\r
 \r
   switch (Node->Bar) {\r

-\r
-  case P2C_BAR_0:\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
-                 1,\r
-                 &Address\r
-                 );\r
-\r
-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    break;\r
-\r
-  case P2C_MEM_1:\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_MEMORY_BASE_0,\r
-                 1,\r
-                 &Address\r
-                 );\r
-\r
-    TempAddress = Address + Node->Length - 1;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_MEMORY_LIMIT_0,\r
-                 1,\r
-                 &TempAddress\r
-                 );\r
-\r
-    if (Node->ResType == PciBarTypeMem32) {\r
-      //\r
-      // Set non-prefetchable bit\r
-      //\r
-      PciIo->Pci.Read (\r
+    case P2C_BAR_0:\r
+      PciIo->Pci.Write (\r

                    PciIo,\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   (Node->PciDev->PciBar[Node->Bar]).Offset,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &Address\r

                    );\r
 \r
                    );\r
 \r

-      BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      break;\r
+\r
+    case P2C_MEM_1:\r

       PciIo->Pci.Write (\r
                    PciIo,\r
       PciIo->Pci.Write (\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_MEMORY_BASE_0,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &Address\r

                    );\r
 \r
                    );\r
 \r

-    } else {\r
-      //\r
-      // Set pre-fetchable bit\r
-      //\r
-      PciIo->Pci.Read (\r
+      TempAddress = Address + Node->Length - 1;\r
+      PciIo->Pci.Write (\r

                    PciIo,\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_MEMORY_LIMIT_0,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &TempAddress\r

                    );\r
 \r
                    );\r
 \r

-      BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
+      if (Node->ResType == PciBarTypeMem32) {\r
+        //\r
+        // Set non-prefetchable bit\r
+        //\r
+        PciIo->Pci.Read (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+\r
+        BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
+        PciIo->Pci.Write (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+      } else {\r
+        //\r
+        // Set prefetchable bit\r
+        //\r
+        PciIo->Pci.Read (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+\r
+        BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
+        PciIo->Pci.Write (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+      }\r
+\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
+\r
+      break;\r
+\r
+    case P2C_MEM_2:\r

       PciIo->Pci.Write (\r
                    PciIo,\r
       PciIo->Pci.Write (\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_MEMORY_BASE_1,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &Address\r

                    );\r
                    );\r

-    }\r

 \r
 \r

-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
+      TempAddress = Address + Node->Length - 1;\r

 \r
 \r

-    break;\r
-\r
-  case P2C_MEM_2:\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_MEMORY_BASE_1,\r
-                 1,\r
-                 &Address\r
-                 );\r
-\r
-    TempAddress = Address + Node->Length - 1;\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_MEMORY_LIMIT_1,\r
+                   1,\r
+                   &TempAddress\r
+                   );\r

 \r
 \r

-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_MEMORY_LIMIT_1,\r
-                 1,\r
-                 &TempAddress\r
-                 );\r
+      if (Node->ResType == PciBarTypeMem32) {\r
+        //\r
+        // Set non-prefetchable bit\r
+        //\r
+        PciIo->Pci.Read (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+\r
+        BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
+        PciIo->Pci.Write (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+      } else {\r
+        //\r
+        // Set prefetchable bit\r
+        //\r
+        PciIo->Pci.Read (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+\r
+        BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
+        PciIo->Pci.Write (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PCI_CARD_BRIDGE_CONTROL,\r
+                     1,\r
+                     &BridgeControl\r
+                     );\r
+      }\r

 \r
 \r

-    if (Node->ResType == PciBarTypeMem32) {\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
+      break;\r

 \r
 \r

-      //\r
-      // Set non-prefetchable bit\r
-      //\r
-      PciIo->Pci.Read (\r
+    case P2C_IO_1:\r
+      PciIo->Pci.Write (\r

                    PciIo,\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_IO_BASE_0_LOWER,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &Address\r

                    );\r
 \r
                    );\r
 \r

-      BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
+      TempAddress = Address + Node->Length - 1;\r

       PciIo->Pci.Write (\r
                    PciIo,\r
       PciIo->Pci.Write (\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_IO_LIMIT_0_LOWER,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &TempAddress\r

                    );\r
 \r
                    );\r
 \r

-    } else {\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r

 \r
 \r

-      //\r
-      // Set pre-fetchable bit\r
-      //\r
-      PciIo->Pci.Read (\r
+      break;\r
+\r
+    case P2C_IO_2:\r
+      PciIo->Pci.Write (\r

                    PciIo,\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_IO_BASE_1_LOWER,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &Address\r

                    );\r
 \r
                    );\r
 \r

-      BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
+      TempAddress = Address + Node->Length - 1;\r

       PciIo->Pci.Write (\r
                    PciIo,\r
       PciIo->Pci.Write (\r
                    PciIo,\r

-                   EfiPciIoWidthUint16,\r
-                   PCI_CARD_BRIDGE_CONTROL,\r
+                   EfiPciIoWidthUint32,\r
+                   PCI_CARD_IO_LIMIT_1_LOWER,\r

                    1,\r
                    1,\r

-                   &BridgeControl\r
+                   &TempAddress\r

                    );\r
                    );\r

-    }\r
-\r
-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
-    break;\r
-\r
-  case P2C_IO_1:\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_IO_BASE_0_LOWER,\r
-                 1,\r
-                 &Address\r
-                 );\r
-\r
-    TempAddress = Address + Node->Length - 1;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_IO_LIMIT_0_LOWER,\r
-                 1,\r
-                 &TempAddress\r
-                 );\r
-\r
-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
-\r
-    break;\r
-\r
-  case P2C_IO_2:\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_IO_BASE_1_LOWER,\r
-                 1,\r
-                 &Address\r
-                 );\r

 \r
 \r

-    TempAddress = Address + Node->Length - 1;\r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PCI_CARD_IO_LIMIT_1_LOWER,\r
-                 1,\r
-                 &TempAddress\r
-                 );\r
-\r
-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
-    Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
-    break;\r
+      Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+      Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+      Node->PciDev->PciBar[Node->Bar].BarType     = Node->ResType;\r
+      break;\r

 \r
 \r

-  default:\r
-    break;\r
+    default:\r
+      break;\r

   }\r
 }\r
 \r
   }\r
 }\r
 \r


@@ -2107,34 +2116,32 @@ ProgramP2C (
 **/\r
 VOID\r
 ApplyResourcePadding (\r
 **/\r
 VOID\r
 ApplyResourcePadding (\r

-  IN PCI_IO_DEVICE         *PciDev,\r
-  IN PCI_RESOURCE_NODE     *IoNode,\r
-  IN PCI_RESOURCE_NODE     *Mem32Node,\r
-  IN PCI_RESOURCE_NODE     *PMem32Node,\r
-  IN PCI_RESOURCE_NODE     *Mem64Node,\r
-  IN PCI_RESOURCE_NODE     *PMem64Node\r
+  IN PCI_IO_DEVICE      *PciDev,\r
+  IN PCI_RESOURCE_NODE  *IoNode,\r
+  IN PCI_RESOURCE_NODE  *Mem32Node,\r
+  IN PCI_RESOURCE_NODE  *PMem32Node,\r
+  IN PCI_RESOURCE_NODE  *Mem64Node,\r
+  IN PCI_RESOURCE_NODE  *PMem64Node\r

   )\r
 {\r
   )\r
 {\r

-  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
-  PCI_RESOURCE_NODE                 *Node;\r
-  UINT8                             DummyBarIndex;\r
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Ptr;\r
+  PCI_RESOURCE_NODE                  *Node;\r
+  UINT8                              DummyBarIndex;\r

 \r
   DummyBarIndex = 0;\r
   Ptr           = PciDev->ResourcePaddingDescriptors;\r
 \r
 \r
   DummyBarIndex = 0;\r
   Ptr           = PciDev->ResourcePaddingDescriptors;\r
 \r

-  while (((EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
-\r
-    if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) {\r
+  while (((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
+    if ((Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO)) {\r

       if (Ptr->AddrLen != 0) {\r
       if (Ptr->AddrLen != 0) {\r

-\r

         Node = CreateResourceNode (\r
         Node = CreateResourceNode (\r

-                PciDev,\r
-                Ptr->AddrLen,\r
-                Ptr->AddrRangeMax,\r
-                DummyBarIndex,\r
-                PciBarTypeIo16,\r
-                PciResUsagePadding\r
-                );\r
+                 PciDev,\r
+                 Ptr->AddrLen,\r
+                 Ptr->AddrRangeMax,\r
+                 DummyBarIndex,\r
+                 PciBarTypeIo16,\r
+                 PciResUsagePadding\r
+                 );\r

         InsertResourceNode (\r
           IoNode,\r
           Node\r
         InsertResourceNode (\r
           IoNode,\r
           Node\r


@@ -2145,23 +2152,21 @@ ApplyResourcePadding (
       continue;\r
     }\r
 \r
       continue;\r
     }\r
 \r

-    if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
-\r
+    if ((Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM)) {\r

       if (Ptr->AddrSpaceGranularity == 32) {\r
       if (Ptr->AddrSpaceGranularity == 32) {\r

-\r

         //\r
         //\r

-        // prefechable\r
+        // prefetchable\r

         //\r
         if (Ptr->SpecificFlag == 0x6) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r
         //\r
         if (Ptr->SpecificFlag == 0x6) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r

-                    PciDev,\r
-                    Ptr->AddrLen,\r
-                    Ptr->AddrRangeMax,\r
-                    DummyBarIndex,\r
-                    PciBarTypePMem32,\r
-                    PciResUsagePadding\r
-                    );\r
+                     PciDev,\r
+                     Ptr->AddrLen,\r
+                     Ptr->AddrRangeMax,\r
+                     DummyBarIndex,\r
+                     PciBarTypePMem32,\r
+                     PciResUsagePadding\r
+                     );\r

             InsertResourceNode (\r
               PMem32Node,\r
               Node\r
             InsertResourceNode (\r
               PMem32Node,\r
               Node\r


@@ -2173,18 +2178,18 @@ ApplyResourcePadding (
         }\r
 \r
         //\r
         }\r
 \r
         //\r

-        // Non-prefechable\r
+        // Non-prefetchable\r

         //\r
         if (Ptr->SpecificFlag == 0) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r
         //\r
         if (Ptr->SpecificFlag == 0) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r

-                    PciDev,\r
-                    Ptr->AddrLen,\r
-                    Ptr->AddrRangeMax,\r
-                    DummyBarIndex,\r
-                    PciBarTypeMem32,\r
-                    PciResUsagePadding\r
-                    );\r
+                     PciDev,\r
+                     Ptr->AddrLen,\r
+                     Ptr->AddrRangeMax,\r
+                     DummyBarIndex,\r
+                     PciBarTypeMem32,\r
+                     PciResUsagePadding\r
+                     );\r

             InsertResourceNode (\r
               Mem32Node,\r
               Node\r
             InsertResourceNode (\r
               Mem32Node,\r
               Node\r


@@ -2197,20 +2202,19 @@ ApplyResourcePadding (
       }\r
 \r
       if (Ptr->AddrSpaceGranularity == 64) {\r
       }\r
 \r
       if (Ptr->AddrSpaceGranularity == 64) {\r

-\r

         //\r
         //\r

-        // prefechable\r
+        // prefetchable\r

         //\r
         if (Ptr->SpecificFlag == 0x6) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r
         //\r
         if (Ptr->SpecificFlag == 0x6) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r

-                    PciDev,\r
-                    Ptr->AddrLen,\r
-                    Ptr->AddrRangeMax,\r
-                    DummyBarIndex,\r
-                    PciBarTypePMem64,\r
-                    PciResUsagePadding\r
-                    );\r
+                     PciDev,\r
+                     Ptr->AddrLen,\r
+                     Ptr->AddrRangeMax,\r
+                     DummyBarIndex,\r
+                     PciBarTypePMem64,\r
+                     PciResUsagePadding\r
+                     );\r

             InsertResourceNode (\r
               PMem64Node,\r
               Node\r
             InsertResourceNode (\r
               PMem64Node,\r
               Node\r


@@ -2222,18 +2226,18 @@ ApplyResourcePadding (
         }\r
 \r
         //\r
         }\r
 \r
         //\r

-        // Non-prefechable\r
+        // Non-prefetchable\r

         //\r
         if (Ptr->SpecificFlag == 0) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r
         //\r
         if (Ptr->SpecificFlag == 0) {\r
           if (Ptr->AddrLen != 0) {\r
             Node = CreateResourceNode (\r

-                    PciDev,\r
-                    Ptr->AddrLen,\r
-                    Ptr->AddrRangeMax,\r
-                    DummyBarIndex,\r
-                    PciBarTypeMem64,\r
-                    PciResUsagePadding\r
-                    );\r
+                     PciDev,\r
+                     Ptr->AddrLen,\r
+                     Ptr->AddrRangeMax,\r
+                     DummyBarIndex,\r
+                     PciBarTypeMem64,\r
+                     PciResUsagePadding\r
+                     );\r

             InsertResourceNode (\r
               Mem64Node,\r
               Node\r
             InsertResourceNode (\r
               Mem64Node,\r
               Node\r


@@ -2260,13 +2264,12 @@ ApplyResourcePadding (
 **/\r
 VOID\r
 GetResourcePaddingPpb (\r
 **/\r
 VOID\r
 GetResourcePaddingPpb (\r

-  IN  PCI_IO_DEVICE                  *PciIoDevice\r
+  IN  PCI_IO_DEVICE  *PciIoDevice\r

   )\r
 {\r
   )\r
 {\r

-  if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+  if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r

     if (PciIoDevice->ResourcePaddingDescriptors == NULL) {\r
       GetResourcePaddingForHpb (PciIoDevice);\r
     }\r
   }\r
 }\r
     if (PciIoDevice->ResourcePaddingDescriptors == NULL) {\r
       GetResourcePaddingForHpb (PciIoDevice);\r
     }\r
   }\r
 }\r

-\r