+ ## If TRUE, then 16550 serial port registers are in MMIO space. \r
+ # If FALSE, then 16550 serial port registers are in I/O space. Default value.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE|BOOLEAN|0x00020000\r
+ \r
+ ## If TRUE, then the 16550 serial port hardware flow control is enabled.\r
+ # If FALSE, then the 16550 serial port hardware flow control is disabled. Default value.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE|BOOLEAN|0x00020001\r
+\r
+ ## If TRUE, then 16550 serial Tx operations will block if DSR is not asserted (no cable).\r
+ # If FALSE, then the 16550 serial Tx operations will not be blocked if DSR is not asserted. Default value.\r
+ # This PCD is ignored if PcdSerialUseHardwareFlowControl is FALSE.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE|BOOLEAN|0x00020006\r
+ \r
+ ## Base address of 16550 serial port registers in MMIO or I/O space. Default is 0x3F8.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8|UINT64|0x00020002\r
+\r
+ ## Baud rate for the 16550 serial port. Default is 115200 baud.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200|UINT32|0x00020003\r
+\r
+ ## Line Control Register (LCR) for the 16550 serial port. This encodes data bits, parity, and stop bits. \r
+ # BIT1..BIT0 - Data bits. 00b = 5 bits, 01b = 6 bits, 10b = 7 bits, 11b = 8 bits\r
+ # BIT2 - Stop Bits. 0 = 1 stop bit. 1 = 1.5 stop bits if 5 data bits selected, otherwise 2 stop bits.\r
+ # BIT5..BIT2 - Parity. xx0b = No Parity, 001b = Odd Parity, 011b = Even Parity, 101b = Mark Parity, 111b=Stick Parity\r
+ # BIT7..BIT6 - Reserved. Must be 0.\r
+ #\r
+ # Default is No Parity, 8 Data Bits, 1 Stop Bit.\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03|UINT8|0x00020004\r
+\r
+ ## FIFO Control Register (FCR) for the 16550 serial port. \r
+ # BIT0 - FIFO Enable. 0 = Disable FIFOs. 1 = Enable FIFOs.\r
+ # BIT1 - Clear receive FIFO. 1 = Clear FIFO.\r
+ # BIT2 - Clear transmit FIFO. 1 = Clear FIFO.\r
+ # BIT7..BIT3 - Reserved. Must be 0.\r
+ #\r
+ # Default is to enable and clear all FIFOs.\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07|UINT8|0x00020005\r
+\r
+ ## Maximum address that the DXE Core will allocate the EFI_SYSTEM_TABLE_POINTER\r
+ # structure. The default value for this PCD is 0, which means that the DXE Core\r
+ # will allocate the buffer from the EFI_SYSTEM_TABLE_POINTER structure on a 4MB\r
+ # boundary as close to the top of memory as feasible. If this PCD is set to a \r
+ # value other than 0, then the DXE Core will first attempt to allocate the \r
+ # EFI_SYSTEM_TABLE_POINTER structure on a 4MB boundary below the address specified\r
+ # by this PCD, and if that allocation fails, retry the allocation on a 4MB\r
+ # boundary as close to the top of memory as feasible.\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxEfiSystemTablePointerAddress|0x0|UINT64|0x30001027\r
+ \r