+ ## FFS filename to find the ACPI tables.\r
+ # @Prompt FFS name of ACPI tables storage.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile|{ 0x25, 0x4e, 0x37, 0x7e, 0x01, 0x8e, 0xee, 0x4f, 0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd }|VOID*|0x30000016\r
+\r
+ ## FFS filename to find the capsule coalesce image.\r
+ # @Prompt FFS name of capsule coalesce image.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile|{ 0xA6, 0xE4, 0xFD, 0xF7, 0x4C, 0x29, 0x3c, 0x49, 0xB5, 0x0F, 0x97, 0x34, 0x55, 0x3B, 0xB7, 0x57 }|VOID*|0x30000017\r
+\r
+ ## Maximum number of performance log entries during PEI phase.\r
+ # @Prompt Maximum number of PEI performance log entries.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f\r
+\r
+ ## RTC Update Timeout Value(microsecond).\r
+ # @Prompt RTC Update Timeout Value.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|100000|UINT32|0x00010034\r
+\r
+ ## Indicates the 16550 serial port registers are in MMIO space, or in I/O space. Default is I/O space.<BR><BR>\r
+ # TRUE - 16550 serial port registers are in MMIO space.<BR>\r
+ # FALSE - 16550 serial port registers are in I/O space.<BR>\r
+ # @Prompt Serial port registers use MMIO.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE|BOOLEAN|0x00020000\r
+\r
+ ## Indicates if the 16550 serial port hardware flow control will be enabled. Default is FALSE.<BR><BR>\r
+ # TRUE - 16550 serial port hardware flow control will be enabled.<BR>\r
+ # FALSE - 16550 serial port hardware flow control will be disabled.<BR>\r
+ # @Prompt Enable serial port hardware flow control.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE|BOOLEAN|0x00020001\r
+\r
+ ## Indicates if the 16550 serial Tx operations will be blocked if DSR is not asserted (no cable). Default is FALSE.\r
+ # This PCD is ignored if PcdSerialUseHardwareFlowControl is FALSE.<BR><BR>\r
+ # TRUE - 16550 serial Tx operations will be blocked if DSR is not asserted.<BR>\r
+ # FALSE - 16550 serial Tx operations will not be blocked if DSR is not asserted.<BR>\r
+ # @Prompt Enable serial port cable detetion.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE|BOOLEAN|0x00020006\r
+ \r
+ ## Base address of 16550 serial port registers in MMIO or I/O space. Default is 0x3F8.\r
+ # @Prompt Base address of serial port registers.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8|UINT64|0x00020002\r
+\r
+ ## Baud rate for the 16550 serial port. Default is 115200 baud.\r
+ # @Prompt Baud rate for serial port.\r
+ # @ValidList 0x80000001 | 921600, 460800, 230400, 115200, 57600, 38400, 19200, 9600, 7200, 4800, 3600, 2400, 2000, 1800, 1200, 600, 300, 150, 134, 110, 75, 50\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200|UINT32|0x00020003\r
+\r
+ ## Line Control Register (LCR) for the 16550 serial port. This encodes data bits, parity, and stop bits.<BR><BR>\r
+ # BIT1..BIT0 - Data bits. 00b = 5 bits, 01b = 6 bits, 10b = 7 bits, 11b = 8 bits<BR>\r
+ # BIT2 - Stop Bits. 0 = 1 stop bit. 1 = 1.5 stop bits if 5 data bits selected, otherwise 2 stop bits.<BR>\r
+ # BIT5..BIT3 - Parity. xx0b = No Parity, 001b = Odd Parity, 011b = Even Parity, 101b = Mark Parity, 111b=Stick Parity<BR>\r
+ # BIT7..BIT6 - Reserved. Must be 0.<BR>\r
+ #\r
+ # Default is No Parity, 8 Data Bits, 1 Stop Bit.<BR>\r
+ # @Prompt Serial port Line Control settings.\r
+ # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl & 0xC0) == 0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03|UINT8|0x00020004\r
+\r
+ ## FIFO Control Register (FCR) for the 16550 serial port.<BR><BR>\r
+ # BIT0 - FIFO Enable. 0 = Disable FIFOs. 1 = Enable FIFOs.<BR>\r
+ # BIT1 - Clear receive FIFO. 1 = Clear FIFO.<BR>\r
+ # BIT2 - Clear transmit FIFO. 1 = Clear FIFO.<BR>\r
+ # BIT4..BIT3 - Reserved. Must be 0.<BR>\r
+ # BIT5 - Enable 64-byte FIFO. 0 = Disable 64-byte FIFO. 1 = Enable 64-byte FIFO<BR>\r
+ # BIT7..BIT6 - Reserved. Must be 0.<BR>\r
+ #\r
+ # Default is to enable and clear all FIFOs.<BR>\r
+ # @Prompt Serial port FIFO Control settings.\r
+ # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl & 0xD8) == 0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07|UINT8|0x00020005\r
+\r
+ ## This setting can override the default TFTP block size. A value of 0 computes\r
+ # the default from MTU information. A non-zero value will be used as block size\r
+ # in bytes.\r
+ # @Prompt TFTP block size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTftpBlockSize|0x0|UINT64|0x30001026\r
+\r
+ ## Maximum address that the DXE Core will allocate the EFI_SYSTEM_TABLE_POINTER\r
+ # structure. The default value for this PCD is 0, which means that the DXE Core\r
+ # will allocate the buffer from the EFI_SYSTEM_TABLE_POINTER structure on a 4MB\r
+ # boundary as close to the top of memory as feasible. If this PCD is set to a \r
+ # value other than 0, then the DXE Core will first attempt to allocate the\r
+ # EFI_SYSTEM_TABLE_POINTER structure on a 4MB boundary below the address specified\r
+ # by this PCD, and if that allocation fails, retry the allocation on a 4MB\r
+ # boundary as close to the top of memory as feasible.\r
+ # @Prompt Maximum Efi System Table Pointer address.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxEfiSystemTablePointerAddress|0x0|UINT64|0x30001027\r
+\r
+ ## Indicates if to shadow PEIM on S3 boot path after memory is ready.<BR><BR>\r
+ # TRUE - Shadow PEIM on S3 boot path after memory is ready.<BR>\r
+ # FALSE - Not shadow PEIM on S3 boot path after memory is ready.<BR>\r
+ # @Prompt Shadow Peim On S3 Boot. \r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|FALSE|BOOLEAN|0x30001028\r
+\r
+ ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to follow ACPI specification.\r
+ # @Prompt Default OEM ID for ACPI table creation.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034\r
+\r
+ ## Default OEM Table ID for ACPI table creation, it is "EDK2 ".\r
+ # @Prompt Default OEM Table ID for ACPI table creation.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x30001035\r
+\r
+ ## Default OEM Revision for ACPI table creation.\r
+ # @Prompt Default OEM Revision for ACPI table creation.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001036\r
+\r
+ ## Default Creator ID for ACPI table creation.\r
+ # @Prompt Default Creator ID for ACPI table creation.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037\r
+\r
+ ## Default Creator Revision for ACPI table creation.\r
+ # @Prompt Default Creator Revision for ACPI table creation.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038\r
+\r
+ ## The mask is used to control memory profile behavior.<BR><BR>\r
+ # BIT0 - Enable UEFI memory profile.<BR>\r
+ # BIT1 - Enable SMRAM profile.<BR>\r
+ # @Prompt Memory Profile Property.\r
+ # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask & 0xFC) == 0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask|0x0|UINT8|0x30001041\r
+\r
+ ## This flag is to control which memory types of alloc info will be recorded by DxeCore & SmmCore.<BR><BR>\r
+ # For SmmCore, only EfiRuntimeServicesCode and EfiRuntimeServicesData are valid.<BR>\r
+ #\r
+ # Below is bit mask for this PCD: (Order is same as UEFI spec)<BR>\r
+ # EfiReservedMemoryType 0x0001<BR>\r
+ # EfiLoaderCode 0x0002<BR>\r
+ # EfiLoaderData 0x0004<BR>\r
+ # EfiBootServicesCode 0x0008<BR>\r
+ # EfiBootServicesData 0x0010<BR>\r
+ # EfiRuntimeServicesCode 0x0020<BR>\r
+ # EfiRuntimeServicesData 0x0040<BR>\r
+ # EfiConventionalMemory 0x0080<BR>\r
+ # EfiUnusableMemory 0x0100<BR>\r
+ # EfiACPIReclaimMemory 0x0200<BR>\r
+ # EfiACPIMemoryNVS 0x0400<BR>\r
+ # EfiMemoryMappedIO 0x0800<BR>\r
+ # EfiMemoryMappedIOPortSpace 0x1000<BR>\r
+ # EfiPalCode 0x2000<BR>\r
+ # OS Reserved 0x8000000000000000<BR>\r
+ #\r
+ # e.g. Reserved+ACPINvs+ACPIReclaim+RuntimeCode+RuntimeData are needed, 0x661 should be used.<BR>\r
+ #\r
+ # @Prompt Memory profile memory type.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfileMemoryType|0x0|UINT64|0x30001042\r
+\r
+ ## UART clock frequency is for the baud rate configuration.\r
+ # @Prompt Serial Port Clock Rate.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|1843200|UINT32|0x00010066\r
+ \r
+ ## PCI Serial Device Info. It is an array of Device, Function, and Power Management\r
+ # information that describes the path that contains zero or more PCI to PCI briges \r
+ # followed by a PCI serial device. Each array entry is 4-bytes in length. The \r
+ # first byte is the PCI Device Number, then second byte is the PCI Function Number, \r
+ # and the last two bytes are the offset to the PCI power management capabilities \r
+ # register used to manage the D0-D3 states. If a PCI power management capabilities \r
+ # register is not present, then the last two bytes in the offset is set to 0. The \r
+ # array is terminated by an array entry with a PCI Device Number of 0xFF. For a \r
+ # non-PCI fixed address serial device, such as an ISA serial device, the value is 0xFF.\r
+ # @Prompt Pci Serial Device Info\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF}|VOID*|0x00010067\r
+\r
+ ## Serial Port Extended Transmit FIFO Size. The default is 64 bytes. \r
+ # @Prompt Serial Port Extended Transmit FIFO Size in Bytes\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|64|UINT32|0x00010068\r
+ \r
+[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
+ ## This PCD defines the Console output row. The default value is 25 according to UEFI spec.\r
+ # This PCD could be set to 0 then console output would be at max column and max row.\r
+ # @Prompt Console output row.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|25|UINT32|0x40000006\r
+\r
+ ## This PCD defines the Console output row. The default value is 80 according to UEFI spec.\r
+ # This PCD could be set to 0 then console output would be at max column and max row.\r
+ # @Prompt Console output column.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|80|UINT32|0x40000007\r
+\r
+ ## This PCD defines the video horizontal resolution.\r
+ # If this PCD is set to 0 then video resolution would be at highest resolution.\r
+ # @Prompt Video horizontal resolution.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800|UINT32|0x40000009\r
+\r
+ ## This PCD defines the video vertical resolution.\r
+ # If this PCD is set to 0 then video resolution would be at highest resolution.\r
+ # @Prompt Video vertical resolution.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600|UINT32|0x4000000a\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
+ ## Base address of the NV variable range in flash device.\r
+ # @Prompt Base address of flash NV variable range.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0|UINT32|0x30000001\r
+\r
+ ## Size of the NV variable range. Note that this value should less than or equal to PcdFlashNvStorageFtwSpareSize.\r
+ # The root cause is that variable driver will use FTW protocol to reclaim variable region.\r
+ # If the length of variable region is larger than FTW spare size, it means the whole variable region can not\r
+ # be reflushed through the manner of fault tolerant write.\r
+ # @Prompt Size of flash NV variable range.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0|UINT32|0x30000002\r
+\r
+ ## Base address of the FTW spare block range in flash device. Note that this value should be block size aligned.\r
+ # @Prompt Base address of flash FTW spare block range.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0|UINT32|0x30000013\r
+\r
+ ## Size of the FTW spare block range. Note that this value should larger than PcdFlashNvStorageVariableSize and block size aligned.\r