-\r
-/**\r
-\r
- @param EnableBerrPromotion Bit63. Enable BERR promotion. When\r
- 1, the Bus Error (BERR) signal is\r
- promoted to the Bus Initialization\r
- (BINIT) signal, and the BINIT pin\r
- is asserted on the occurrence of\r
- each Bus Error. Setting this bit\r
- has no effect if BINIT signalling\r
- is disabled. (See\r
- PAL_BUS_GET/SET_FEATURES)\r
-\r
- @param EnableMcaPromotion Bit62, Enable MCA promotion. When\r
- 1, machine check aborts (MCAs) are\r
- promoted to the Bus Error signal,\r
- and the BERR pin is assert on each\r
- occurrence of an MCA. Setting this\r
- bit has no effect if BERR\r
- signalling is disabled. (See\r
- PAL_BUS_GET/SET_FEATURES)\r
-\r
- @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT\r
- promotion. When 1, machine\r
- check aborts (MCAs) are\r
- promoted to the Bus\r
- Initialization signal, and\r
- the BINIT pin is assert on\r
- each occurrence of an MCA.\r
- Setting this bit has no\r
- effect if BINIT signalling\r
- is disabled. (See\r
- PAL_BUS_GET/SET_FEATURES)\r
-\r
- @param EnableCmciPromotion Bit60, Enable CMCI promotion When\r
- 1, Corrected Machine Check\r
- Interrupts (CMCI) are promoted to\r
- MCAs. They are also further\r
- promoted to BERR if bit 39, Enable\r
- MCA promotion, is also set and\r
- they are promoted to BINIT if bit\r
- 38, Enable MCA to BINIT promotion,\r
- is also set. This bit has no\r
- effect if MCA signalling is\r
- disabled (see\r
- PAL_BUS_GET/SET_FEATURES)\r
-\r
- @param DisableCache Bit59, Disable Cache. When 0, the\r
- processor performs cast outs on\r
- cacheable pages and issues and responds\r
- to coherency requests normally. When 1,\r
- the processor performs a memory access\r
- for each reference regardless of cache\r
- contents and issues no coherence\r
- requests and responds as if the line\r
- were not present. Cache contents cannot\r
- be relied upon when the cache is\r
- disabled. WARNING: Semaphore\r
- instructions may not be atomic or may\r
- cause Unsupported Data Reference faults\r
- if caches are disabled.\r
-\r
- @param DisableCoherency Bit58, Disable Coherency. When 0,\r
- the processor uses normal coherency\r
- requests and responses. When 1, the\r
- processor answers all requests as if\r
- the line were not present.\r
-\r
- @param DisableDPM Bit57, Disable Dynamic Power Management\r
- (DPM). When 0, the hardware may reduce\r
- power consumption by removing the clock\r
- input from idle functional units. When 1,\r
- all functional units will receive clock\r
- input, even when idle.\r
-\r
- @param DisableBinitWithTimeout Bit56, Disable a BINIT on\r
- internal processor time-out.\r
- When 0, the processor may\r
- generate a BINIT on an\r
- internal processor time-out.\r
- When 1, the processor will not\r
- generate a BINIT on an\r
- internal processor time-out.\r
- The event is silently ignored.\r
-\r
-\r
- @param EnableEnvNotification Bit55, Enable external\r
- notification when the processor\r
- detects hardware errors caused\r
- by environmental factors that\r
- could cause loss of\r
- deterministic behavior of the\r
- processor. When 1, this bit will\r
- enable external notification,\r
- when 0 external notification is\r
- not provided. The type of\r
- external notification of these\r
- errors is processor-dependent. A\r
- loss of processor deterministic\r
- behavior is considered to have\r
- occurred if these\r
- environmentally induced errors\r
- cause the processor to deviate\r
- from its normal execution and\r
- eventually causes different\r
- behavior which can be observed\r
- at the processor bus pins.\r
- Processor errors that do not\r
- have this effects (i.e.,\r
- software induced machine checks)\r
- may or may not be promoted\r
- depending on the processor\r
- implementation.\r
-\r
- @param EnableVmsw Bit54, Enable the use of the vmsw\r
- instruction. When 0, the vmsw instruction\r
- causes a Virtualization fault when\r
- executed at the most privileged level.\r
- When 1, this bit will enable normal\r
- operation of the vmsw instruction.\r
-\r
- @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling\r
- on data-poisoning event\r
- detection. When 0, a CMCI\r
- will be signaled on error\r
- detection. When 1, an MCA\r
- will be signaled on error\r
- detection. If this feature\r
- is not supported, then the\r
- corresponding argument is\r
- ignored when calling\r
- PAL_PROC_SET_FEATURES. Note\r
- that the functionality of\r
- this bit is independent of\r
- the setting in bit 60\r
- (Enable CMCI promotion), and\r
- that the bit 60 setting does\r
- not affect CMCI signaling\r
- for data-poisoning related\r
- events. Volume 2: Processor\r
- Abstraction Layer 2:431\r
- PAL_PROC_GET_FEATURES\r
-\r
- @param DisablePState Bit52, Disable P-states. When 1, the PAL\r
- P-state procedures (PAL_PSTATE_INFO,\r
- PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
- return with a status of -1\r
- (Unimplemented procedure).\r
-\r
- @param DisableBranchPrediction Bit47, Disable Dynamic branch\r
- prediction. When 0, the\r
- processor may predict branch\r
- targets and speculatively\r
- execute, but may not commit\r
- results. When 1, the processor\r
- must wait until branch targets\r
- are known to execute.\r
-\r
- @param DisableDynamicInsCachePrefetch Bit46, Disable\r
- DynamicInstruction Cache\r
- Prefetch. When 0, the\r
- processor may prefetch\r
- into the caches any\r
- instruction which has\r
- not been executed, but\r
- whose execution is\r
- likely. When 1,\r
- instructions may not be\r
- fetched until needed or\r
- hinted for execution.\r
- (Prefetch for a hinted\r
- branch is allowed even\r
- when dynamic instruction\r
- cache prefetch is\r
- disabled.)\r
-\r
- @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic\r
- Data Cache Prefetch.\r
- When 0, the processor\r
- may prefetch into the\r
- caches any data which\r
- has not been accessed\r
- by instruction\r
- execution, but which\r
- is likely to be\r
- accessed. When 1, no\r
- data may be fetched\r
- until it is needed for\r
- instruction execution\r
- or is fetched by an\r
- lfetch instruction.\r
-\r
- @param DisableSpontaneousDeferral Bit44, Disable Spontaneous\r
- Deferral. When 1, the\r
- processor may optionally\r
- defer speculative loads\r
- that do not encounter any\r
- exception conditions, but\r
- that trigger other\r
- implementation-dependent\r
- conditions (e.g., cache\r
- miss). When 0, spontaneous\r
- deferral is disabled.\r
-\r
- @param DisableDynamicPrediction Bit43, Disable Dynamic\r
- Predicate Prediction. When\r
- 0, the processor may predict\r
- predicate results and\r
- execute speculatively, but\r
- may not commit results until\r
- the actual predicates are\r
- known. When 1, the processor\r
- shall not execute predicated\r
- instructions until the\r
- actual predicates are known.\r
-\r
- @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.\r
- Denotes whether XR1 XR3 are\r
- implemented for machine check\r
- recovery. This feature may only be\r
- interrogated by PAL_PROC_GET_FEATURES.\r
- It may not be enabled or disabled by\r
- PAL_PROC_SET_FEATURES. The\r
- corresponding argument is ignored.\r
-\r
- @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS\r
- implemented. Denotes whether XIP, XPSR,\r
- and XFS are implemented for machine\r
- check recovery. This feature may only be\r
- interrogated by PAL_PROC_GET_FEATURES.\r
- It may not be enabled or disabled by\r
- PAL_PROC_SET_FEATURES. The corresponding\r
- argument is ignored.\r
-\r
- @param NoVM Bit40, No Virtual Machine features implemented.\r
- Denotes whether PSR.vm is implemented. This\r
- feature may only be interrogated by\r
- PAL_PROC_GET_FEATURES. It may not be enabled or\r
- disabled by PAL_PROC_SET_FEATURES. The\r
- corresponding argument is ignored.\r
-\r
- @param NoVariablePState Bit39, No Variable P-state\r
- performance: A value of 1, indicates\r
- that a processor implements\r
- techniques to optimize performance\r
- for the given P-state power budget\r
- by dynamically varying the\r
- frequency, such that maximum\r
- performance is achieved for the\r
- power budget. A value of 0,\r
- indicates that P-states have no\r
- frequency variation or very small\r
- frequency variations for their given\r
- power budget. This feature may only\r
- be interrogated by\r
- PAL_PROC_GET_FEATURES. it may not be\r
- enabled or disabled by\r
- PAL_PROC_SET_FEATURES. The\r
- corresponding argument is ignored.\r
-\r
-\r
- @param NoSimpleImpInUndefinedIns Bit38, No Simple\r
- implementation of\r
- unimplemented instruction\r
- addresses. Denotes how an\r
- unimplemented instruction\r
- address is recorded in IIP\r
- on an Unimplemented\r
- Instruction Address trap or\r
- fault. When 1, the full\r
- unimplemented address is\r
- recorded in IIP; when 0, the\r
- address is sign extended\r
- (virtual addresses) or zero\r
- extended (physical\r
- addresses). This feature may\r
- only be interrogated by\r
- PAL_PROC_GET_FEATURES. It\r
- may not be enabled or\r
- disabled by\r
- PAL_PROC_SET_FEATURES. The\r
- corresponding argument is\r
- ignored.\r
-\r
- @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins\r
- present. Denotes the absence of INIT,\r
- PMI, LINT0 and LINT1 pins on the\r
- processor. When 1, the pins are absent.\r
- When 0, the pins are present. This\r
- feature may only be interrogated by\r
- PAL_PROC_GET_FEATURES. It may not be\r
- enabled or disabled by\r
- PAL_PROC_SET_FEATURES. The corresponding\r
- argument is ignored.\r
-\r
- @param FaultInUndefinedIns Bit36, No Unimplemented\r
- instruction address reported as\r
- fault. Denotes how the processor\r
- reports the detection of\r
- unimplemented instruction\r
- addresses. When 1, the processor\r
- reports an Unimplemented\r
- Instruction Address fault on the\r
- unimplemented address; when 0, it\r
- reports an Unimplemented\r
- Instruction Address trap on the\r
- previous instruction in program\r
- order. This feature may only be\r
- interrogated by\r
- PAL_PROC_GET_FEATURES. It may not\r
- be enabled or disabled by\r
- PAL_PROC_SET_FEATURES. The\r
- corresponding argument is\r
- ignored.\r
-\r
-**/\r