+#include <IndustryStandard/Pci22.h>\r
+\r
+///\r
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
+///\r
+///@{\r
+#define PCI_CLASS_MASS_STORAGE_ATA 0x05\r
+#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20\r
+#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_NETWORK, Base Class 02h.\r
+///\r
+///@{\r
+#define PCI_CLASS_NETWORK_WORLDFIP 0x05\r
+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_BRIDGE, Base Class 06h.\r
+///\r
+///@{\r
+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09\r
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40\r
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80\r
+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_SCC, Base Class 07h.\r
+///\r
+///@{\r
+#define PCI_SUBCLASS_GPIB 0x04\r
+#define PCI_SUBCLASS_SMART_CARD 0x05\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_SERIAL, Base Class 0Ch.\r
+///\r
+///@{\r
+#define PCI_IF_EHCI 0x20\r
+#define PCI_CLASS_SERIAL_IB 0x06\r
+#define PCI_CLASS_SERIAL_IPMI 0x07\r
+#define PCI_IF_IPMI_SMIC 0x00\r
+#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style\r
+#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer\r
+#define PCI_CLASS_SERIAL_SERCOS 0x08\r
+#define PCI_CLASS_SERIAL_CANBUS 0x09\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_WIRELESS, Base Class 0Dh.\r
+///\r
+///@{\r
+#define PCI_SUBCLASS_BLUETOOTH 0x11\r
+#define PCI_SUBCLASS_BROADBAND 0x12\r
+///@}\r