- This function flushes the range of addresses from Start to Start+Length \r
- from the processor's data cache. If Start is not aligned to a cache line \r
- boundary, then the bytes before Start to the preceding cache line boundary \r
- are also flushed. If Start+Length is not aligned to a cache line boundary, \r
- then the bytes past Start+Length to the end of the next cache line boundary \r
- are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
- supported. If the data cache is fully coherent with all DMA operations, then \r
- this function can just return EFI_SUCCESS. If the processor does not support \r
+ This function flushes the range of addresses from Start to Start+Length\r
+ from the processor's data cache. If Start is not aligned to a cache line\r
+ boundary, then the bytes before Start to the preceding cache line boundary\r
+ are also flushed. If Start+Length is not aligned to a cache line boundary,\r
+ then the bytes past Start+Length to the end of the next cache line boundary\r
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
+ supported. If the data cache is fully coherent with all DMA operations, then\r
+ this function can just return EFI_SUCCESS. If the processor does not support\r