MdePkg: Apply uncrustify changes

[mirror_edk2.git] / MdePkg / Library / SmmPciLibPciRootBridgeIo / PciLib.c

diff --git a/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c
index 5d3f6a194add8c36ca67b0444500f4adb0068f94..1503ebb3fdf2a3072ae16e5964c477d2e48e91cb 100644 (file)
--- a/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c
@@ -1,15 +1,8 @@
 /** @file\r
   PCI Library using SMM PCI Root Bridge I/O Protocol.\r
 \r
 /** @file\r
   PCI Library using SMM PCI Root Bridge I/O Protocol.\r
 \r

-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials are\r
-  licensed and made available under the terms and conditions of\r
-  the BSD License which accompanies this distribution.  The full\r
-  text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-  \r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r

 \r
 **/\r
 #include <PiSmm.h>\r
 \r
 **/\r
 #include <PiSmm.h>\r


@@ -19,7 +12,6 @@
 #include <Library/BaseLib.h>\r
 #include <Library/SmmServicesTableLib.h>\r
 \r
 #include <Library/BaseLib.h>\r
 #include <Library/SmmServicesTableLib.h>\r
 \r

-\r

 /**\r
   Assert the validity of a PCI address. A valid PCI address should contain 1's\r
   only in the low 28 bits.\r
 /**\r
   Assert the validity of a PCI address. A valid PCI address should contain 1's\r
   only in the low 28 bits.\r


@@ -28,13 +20,13 @@
   @param  M Additional bits to assert to be zero.\r
 \r
 **/\r
   @param  M Additional bits to assert to be zero.\r
 \r
 **/\r

-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \\r

   ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
 \r
 /**\r
   Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r
 \r
   ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
 \r
 /**\r
   Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r
 \r

-  @param  A  Address that encodes the PCI Bus, Device, Function and\r
+  @param  A  The address that encodes the PCI Bus, Device, Function and\r

              Register.\r
 \r
 **/\r
              Register.\r
 \r
 **/\r


@@ -42,32 +34,32 @@
   ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
 \r
 //\r
   ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
 \r
 //\r

-// Global varible to cache pointer to PCI Root Bridge I/O protocol.\r
+// Global variable to cache pointer to PCI Root Bridge I/O protocol.\r

 //\r
 //\r

-EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL      *mSmmPciRootBridgeIo = NULL; \r
+EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL  *mSmmPciRootBridgeIo = NULL;\r

 \r
 /**\r
   The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r
 \r
 /**\r
   The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r

-  \r
+\r

   The constructor function locates PCI Root Bridge I/O protocol from protocol database.\r
   The constructor function locates PCI Root Bridge I/O protocol from protocol database.\r

-  It will ASSERT() if that operation fails and it will always return EFI_SUCCESS. \r
+  It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r

 \r
   @param  ImageHandle   The firmware allocated handle for the EFI image.\r
   @param  SystemTable   A pointer to the EFI System Table.\r
 \r
   @param  ImageHandle   The firmware allocated handle for the EFI image.\r
   @param  SystemTable   A pointer to the EFI System Table.\r

-  \r
+\r

   @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.\r
 \r
 **/\r
 EFI_STATUS\r
 EFIAPI\r
 PciLibConstructor (\r
   @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.\r
 \r
 **/\r
 EFI_STATUS\r
 EFIAPI\r
 PciLibConstructor (\r

-  IN EFI_HANDLE                ImageHandle,\r
-  IN EFI_SYSTEM_TABLE          *SystemTable\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r

   )\r
 {\r
   EFI_STATUS  Status;\r
   )\r
 {\r
   EFI_STATUS  Status;\r

-  \r
-  Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mSmmPciRootBridgeIo);\r
+\r
+  Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID **)&mSmmPciRootBridgeIo);\r

   ASSERT_EFI_ERROR (Status);\r
   ASSERT (mSmmPciRootBridgeIo != NULL);\r
 \r
   ASSERT_EFI_ERROR (Status);\r
   ASSERT (mSmmPciRootBridgeIo != NULL);\r
 \r


@@ -81,9 +73,9 @@ PciLibConstructor (
   It reads and returns the PCI configuration register specified by Address,\r
   the width of data is specified by Width.\r
 \r
   It reads and returns the PCI configuration register specified by Address,\r
   the width of data is specified by Width.\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
                   Register.\r

-  @param  Width   Width of data to read\r
+  @param  Width   The width of data to read\r

 \r
   @return The value read from the PCI configuration register.\r
 \r
 \r
   @return The value read from the PCI configuration register.\r
 \r


@@ -97,12 +89,12 @@ SmmPciLibPciRootBridgeIoReadWorker (
   UINT32  Data;\r
 \r
   mSmmPciRootBridgeIo->Pci.Read (\r
   UINT32  Data;\r
 \r
   mSmmPciRootBridgeIo->Pci.Read (\r

-                          mSmmPciRootBridgeIo,\r
-                          Width,\r
-                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
-                          1,\r
-                          &Data\r
-                          );\r
+                             mSmmPciRootBridgeIo,\r
+                             Width,\r
+                             PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
+                             1,\r
+                             &Data\r
+                             );\r

 \r
   return Data;\r
 }\r
 \r
   return Data;\r
 }\r


@@ -112,12 +104,12 @@ SmmPciLibPciRootBridgeIoReadWorker (
 \r
   This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r
   It writes the PCI configuration register specified by Address with the\r
 \r
   This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r
   It writes the PCI configuration register specified by Address with the\r

-  value specified by Data. The width of data is specifed by Width.\r
+  value specified by Data. The width of data is specified by Width.\r

   Data is returned.\r
 \r
   Data is returned.\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
                   Register.\r

-  @param  Width   Width of data to write\r
+  @param  Width   The width of data to write\r

   @param  Data    The value to write.\r
 \r
   @return The value written to the PCI configuration register.\r
   @param  Data    The value to write.\r
 \r
   @return The value written to the PCI configuration register.\r


@@ -131,29 +123,29 @@ SmmPciLibPciRootBridgeIoWriteWorker (
   )\r
 {\r
   mSmmPciRootBridgeIo->Pci.Write (\r
   )\r
 {\r
   mSmmPciRootBridgeIo->Pci.Write (\r

-                          mSmmPciRootBridgeIo,\r
-                          Width,\r
-                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
-                          1,\r
-                          &Data\r
-                          );\r
+                             mSmmPciRootBridgeIo,\r
+                             Width,\r
+                             PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
+                             1,\r
+                             &Data\r
+                             );\r

   return Data;\r
 }\r
 \r
 /**\r
   return Data;\r
 }\r
 \r
 /**\r

-  Registers a PCI device so PCI configuration registers may be accessed after \r
+  Registers a PCI device so PCI configuration registers may be accessed after\r

   SetVirtualAddressMap().\r
   SetVirtualAddressMap().\r

-  \r
-  Registers the PCI device specified by Address so all the PCI configuration registers \r
+\r
+  Registers the PCI device specified by Address so all the PCI configuration registers\r

   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r

-  \r
+\r

   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
                   Register.\r

-  \r
+\r

   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r

-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function \r
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function\r

                                    after ExitBootServices().\r
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
                                    at runtime could not be mapped.\r
                                    after ExitBootServices().\r
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
                                    at runtime could not be mapped.\r


@@ -180,7 +172,7 @@ PciRegisterForRuntimeAccess (
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
 \r
   @return The read value from the PCI configuration register.\r
                   Register.\r
 \r
   @return The read value from the PCI configuration register.\r


@@ -189,12 +181,12 @@ PciRegisterForRuntimeAccess (
 UINT8\r
 EFIAPI\r
 PciRead8 (\r
 UINT8\r
 EFIAPI\r
 PciRead8 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
 \r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
 \r

-  return (UINT8) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
+  return (UINT8)SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -206,7 +198,7 @@ PciRead8 (
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  Value   The value to write.\r
 \r
                   Register.\r
   @param  Value   The value to write.\r
 \r


@@ -216,13 +208,13 @@ PciRead8 (
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINT8  Value\r

   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
 \r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
 \r

-  return (UINT8) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
+  return (UINT8)SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -238,7 +230,7 @@ PciWrite8 (
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  OrData  The value to OR with the PCI configuration register.\r
 \r
                   Register.\r
   @param  OrData  The value to OR with the PCI configuration register.\r
 \r


@@ -248,11 +240,11 @@ PciWrite8 (
 UINT8\r
 EFIAPI\r
 PciOr8 (\r
 UINT8\r
 EFIAPI\r
 PciOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  OrData\r

   )\r
 {\r
   )\r
 {\r

-  return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r
+  return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -268,7 +260,7 @@ PciOr8 (
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
 \r
                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
 \r


@@ -278,11 +270,11 @@ PciOr8 (
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData\r

   )\r
 {\r
   )\r
 {\r

-  return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r
+  return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -299,7 +291,7 @@ PciAnd8 (
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
   @param  OrData  The value to OR with the result of the AND operation.\r
                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
   @param  OrData  The value to OR with the result of the AND operation.\r


@@ -310,12 +302,12 @@ PciAnd8 (
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r

   )\r
 {\r
   )\r
 {\r

-  return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r
+  return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -330,7 +322,7 @@ PciAndThenOr8 (
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r

-  @param  Address   PCI configuration register to read.\r
+  @param  Address   The PCI configuration register to read.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -342,9 +334,9 @@ PciAndThenOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   )\r
 {\r
   return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
   )\r
 {\r
   return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r


@@ -362,13 +354,14 @@ PciBitFieldRead8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                     Range 0..7.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                     Range 0..7.\r

-  @param  Value     New value of the bit field.\r
+  @param  Value     The new value of the bit field.\r

 \r
   @return The value written back to the PCI configuration register.\r
 \r
 \r
   @return The value written back to the PCI configuration register.\r
 \r


@@ -376,10 +369,10 @@ PciBitFieldRead8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  Value\r

   )\r
 {\r
   return PciWrite8 (\r
   )\r
 {\r
   return PciWrite8 (\r


@@ -403,8 +396,9 @@ PciBitFieldWrite8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -417,10 +411,10 @@ PciBitFieldWrite8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  OrData\r

   )\r
 {\r
   return PciWrite8 (\r
   )\r
 {\r
   return PciWrite8 (\r


@@ -444,8 +438,9 @@ PciBitFieldOr8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -458,10 +453,10 @@ PciBitFieldOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData\r

   )\r
 {\r
   return PciWrite8 (\r
   )\r
 {\r
   return PciWrite8 (\r


@@ -487,8 +482,10 @@ PciBitFieldAnd8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..7.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -502,11 +499,11 @@ PciBitFieldAnd8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r

   )\r
 {\r
   return PciWrite8 (\r
   )\r
 {\r
   return PciWrite8 (\r


@@ -525,7 +522,7 @@ PciBitFieldAndThenOr8 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
 \r
   @return The read value from the PCI configuration register.\r
                   Register.\r
 \r
   @return The read value from the PCI configuration register.\r


@@ -534,12 +531,12 @@ PciBitFieldAndThenOr8 (
 UINT16\r
 EFIAPI\r
 PciRead16 (\r
 UINT16\r
 EFIAPI\r
 PciRead16 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
 \r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
 \r

-  return (UINT16) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
+  return (UINT16)SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -552,7 +549,7 @@ PciRead16 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  Value   The value to write.\r
 \r
                   Register.\r
   @param  Value   The value to write.\r
 \r


@@ -562,13 +559,13 @@ PciRead16 (
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINT16  Value\r

   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
 \r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
 \r

-  return (UINT16) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
+  return (UINT16)SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -585,7 +582,7 @@ PciWrite16 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  OrData  The value to OR with the PCI configuration register.\r
 \r
                   Register.\r
   @param  OrData  The value to OR with the PCI configuration register.\r
 \r


@@ -595,11 +592,11 @@ PciWrite16 (
 UINT16\r
 EFIAPI\r
 PciOr16 (\r
 UINT16\r
 EFIAPI\r
 PciOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  OrData\r

   )\r
 {\r
   )\r
 {\r

-  return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r
+  return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -616,7 +613,7 @@ PciOr16 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
 \r
                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
 \r


@@ -626,11 +623,11 @@ PciOr16 (
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData\r

   )\r
 {\r
   )\r
 {\r

-  return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r
+  return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -648,7 +645,7 @@ PciAnd16 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
   @param  OrData  The value to OR with the result of the AND operation.\r
                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
   @param  OrData  The value to OR with the result of the AND operation.\r


@@ -659,12 +656,12 @@ PciAnd16 (
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r

   )\r
 {\r
   )\r
 {\r

-  return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r
+  return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -680,7 +677,7 @@ PciAndThenOr16 (
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r

-  @param  Address   PCI configuration register to read.\r
+  @param  Address   The PCI configuration register to read.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -692,9 +689,9 @@ PciAndThenOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   )\r
 {\r
   return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
   )\r
 {\r
   return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r


@@ -713,13 +710,14 @@ PciBitFieldRead16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                     Range 0..15.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                     Range 0..15.\r

-  @param  Value     New value of the bit field.\r
+  @param  Value     The new value of the bit field.\r

 \r
   @return The value written back to the PCI configuration register.\r
 \r
 \r
   @return The value written back to the PCI configuration register.\r
 \r


@@ -727,10 +725,10 @@ PciBitFieldRead16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  Value\r

   )\r
 {\r
   return PciWrite16 (\r
   )\r
 {\r
   return PciWrite16 (\r


@@ -755,8 +753,9 @@ PciBitFieldWrite16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -769,10 +768,10 @@ PciBitFieldWrite16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  OrData\r

   )\r
 {\r
   return PciWrite16 (\r
   )\r
 {\r
   return PciWrite16 (\r


@@ -797,8 +796,9 @@ PciBitFieldOr16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -811,10 +811,10 @@ PciBitFieldOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData\r

   )\r
 {\r
   return PciWrite16 (\r
   )\r
 {\r
   return PciWrite16 (\r


@@ -841,8 +841,10 @@ PciBitFieldAnd16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..15.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -856,11 +858,11 @@ PciBitFieldAnd16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r

   )\r
 {\r
   return PciWrite16 (\r
   )\r
 {\r
   return PciWrite16 (\r


@@ -879,7 +881,7 @@ PciBitFieldAndThenOr16 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
 \r
   @return The read value from the PCI configuration register.\r
                   Register.\r
 \r
   @return The read value from the PCI configuration register.\r


@@ -888,7 +890,7 @@ PciBitFieldAndThenOr16 (
 UINT32\r
 EFIAPI\r
 PciRead32 (\r
 UINT32\r
 EFIAPI\r
 PciRead32 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r


@@ -906,7 +908,7 @@ PciRead32 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  Value   The value to write.\r
 \r
                   Register.\r
   @param  Value   The value to write.\r
 \r


@@ -916,8 +918,8 @@ PciRead32 (
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINT32  Value\r

   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r


@@ -939,7 +941,7 @@ PciWrite32 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  OrData  The value to OR with the PCI configuration register.\r
 \r
                   Register.\r
   @param  OrData  The value to OR with the PCI configuration register.\r
 \r


@@ -949,8 +951,8 @@ PciWrite32 (
 UINT32\r
 EFIAPI\r
 PciOr32 (\r
 UINT32\r
 EFIAPI\r
 PciOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  OrData\r

   )\r
 {\r
   return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
   )\r
 {\r
   return PciWrite32 (Address, PciRead32 (Address) | OrData);\r


@@ -970,7 +972,7 @@ PciOr32 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
 \r
                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
 \r


@@ -980,8 +982,8 @@ PciOr32 (
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData\r

   )\r
 {\r
   return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
   )\r
 {\r
   return PciWrite32 (Address, PciRead32 (Address) & AndData);\r


@@ -1002,7 +1004,7 @@ PciAnd32 (
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
   If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r

-  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+  @param  Address The address that encodes the PCI Bus, Device, Function and\r

                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
   @param  OrData  The value to OR with the result of the AND operation.\r
                   Register.\r
   @param  AndData The value to AND with the PCI configuration register.\r
   @param  OrData  The value to OR with the result of the AND operation.\r


@@ -1013,9 +1015,9 @@ PciAnd32 (
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r

   )\r
 {\r
   return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
   )\r
 {\r
   return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r


@@ -1034,7 +1036,7 @@ PciAndThenOr32 (
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r

-  @param  Address   PCI configuration register to read.\r
+  @param  Address   The PCI configuration register to read.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -1046,9 +1048,9 @@ PciAndThenOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   )\r
 {\r
   return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
   )\r
 {\r
   return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r


@@ -1067,13 +1069,14 @@ PciBitFieldRead32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                     Range 0..31.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                     Range 0..31.\r

-  @param  Value     New value of the bit field.\r
+  @param  Value     The new value of the bit field.\r

 \r
   @return The value written back to the PCI configuration register.\r
 \r
 \r
   @return The value written back to the PCI configuration register.\r
 \r


@@ -1081,10 +1084,10 @@ PciBitFieldRead32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  Value\r

   )\r
 {\r
   return PciWrite32 (\r
   )\r
 {\r
   return PciWrite32 (\r


@@ -1109,8 +1112,9 @@ PciBitFieldWrite32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -1123,10 +1127,10 @@ PciBitFieldWrite32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  OrData\r

   )\r
 {\r
   return PciWrite32 (\r
   )\r
 {\r
   return PciWrite32 (\r


@@ -1151,8 +1155,9 @@ PciBitFieldOr32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -1165,10 +1170,10 @@ PciBitFieldOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData\r

   )\r
 {\r
   return PciWrite32 (\r
   )\r
 {\r
   return PciWrite32 (\r


@@ -1195,8 +1200,10 @@ PciBitFieldAnd32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
 \r

-  @param  Address   PCI configuration register to write.\r
+  @param  Address   The PCI configuration register to write.\r

   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                     Range 0..31.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r


@@ -1210,11 +1217,11 @@ PciBitFieldAnd32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r

   )\r
 {\r
   return PciWrite32 (\r
   )\r
 {\r
   return PciWrite32 (\r


@@ -1230,7 +1237,7 @@ PciBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r

-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r

   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r


@@ -1238,10 +1245,10 @@ PciBitFieldAndThenOr32 (
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r

-  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
+  @param  StartAddress  The starting address that encodes the PCI Bus, Device,\r

                         Function and Register.\r
                         Function and Register.\r

-  @param  Size          Size in bytes of the transfer.\r
-  @param  Buffer        Pointer to a buffer receiving the data read.\r
+  @param  Size          The size in bytes of the transfer.\r
+  @param  Buffer        The pointer to a buffer receiving the data read.\r

 \r
   @return Size\r
 \r
 \r
   @return Size\r
 \r


@@ -1249,12 +1256,12 @@ PciBitFieldAndThenOr32 (
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r

-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  OUT     VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  OUT     VOID   *Buffer\r

   )\r
 {\r
   )\r
 {\r

-  UINTN                             ReturnValue;\r
+  UINTN  ReturnValue;\r

 \r
   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
   ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
 \r
   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
   ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r


@@ -1275,19 +1282,19 @@ PciReadBuffer (
     // Read a byte if StartAddress is byte aligned\r
     //\r
     *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
     // Read a byte if StartAddress is byte aligned\r
     //\r
     *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r

-    StartAddress += sizeof (UINT8);\r
-    Size -= sizeof (UINT8);\r
-    Buffer = (UINT8*)Buffer + 1;\r
+    StartAddress             += sizeof (UINT8);\r
+    Size                     -= sizeof (UINT8);\r
+    Buffer                    = (UINT8 *)Buffer + 1;\r

   }\r
 \r
   }\r
 \r

-  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+  if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r

     //\r
     // Read a word if StartAddress is word aligned\r
     //\r
     WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
     StartAddress += sizeof (UINT16);\r
     //\r
     // Read a word if StartAddress is word aligned\r
     //\r
     WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
     StartAddress += sizeof (UINT16);\r

-    Size -= sizeof (UINT16);\r
-    Buffer = (UINT16*)Buffer + 1;\r
+    Size         -= sizeof (UINT16);\r
+    Buffer        = (UINT16 *)Buffer + 1;\r

   }\r
 \r
   while (Size >= sizeof (UINT32)) {\r
   }\r
 \r
   while (Size >= sizeof (UINT32)) {\r


@@ -1296,8 +1303,8 @@ PciReadBuffer (
     //\r
     WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
     StartAddress += sizeof (UINT32);\r
     //\r
     WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
     StartAddress += sizeof (UINT32);\r

-    Size -= sizeof (UINT32);\r
-    Buffer = (UINT32*)Buffer + 1;\r
+    Size         -= sizeof (UINT32);\r
+    Buffer        = (UINT32 *)Buffer + 1;\r

   }\r
 \r
   if (Size >= sizeof (UINT16)) {\r
   }\r
 \r
   if (Size >= sizeof (UINT16)) {\r


@@ -1306,8 +1313,8 @@ PciReadBuffer (
     //\r
     WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
     StartAddress += sizeof (UINT16);\r
     //\r
     WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
     StartAddress += sizeof (UINT16);\r

-    Size -= sizeof (UINT16);\r
-    Buffer = (UINT16*)Buffer + 1;\r
+    Size         -= sizeof (UINT16);\r
+    Buffer        = (UINT16 *)Buffer + 1;\r

   }\r
 \r
   if (Size >= sizeof (UINT8)) {\r
   }\r
 \r
   if (Size >= sizeof (UINT8)) {\r


@@ -1328,7 +1335,7 @@ PciReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r

-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r

   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r


@@ -1336,10 +1343,10 @@ PciReadBuffer (
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r

-  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
+  @param  StartAddress  The starting address that encodes the PCI Bus, Device,\r

                         Function and Register.\r
                         Function and Register.\r

-  @param  Size          Size in bytes of the transfer.\r
-  @param  Buffer        Pointer to a buffer containing the data to write.\r
+  @param  Size          The size in bytes of the transfer.\r
+  @param  Buffer        The pointer to a buffer containing the data to write.\r

 \r
   @return Size written to StartAddress.\r
 \r
 \r
   @return Size written to StartAddress.\r
 \r


@@ -1347,12 +1354,12 @@ PciReadBuffer (
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r

-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  IN      VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  IN      VOID   *Buffer\r

   )\r
 {\r
   )\r
 {\r

-  UINTN                             ReturnValue;\r
+  UINTN  ReturnValue;\r

 \r
   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
   ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
 \r
   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
   ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r


@@ -1372,20 +1379,20 @@ PciWriteBuffer (
     //\r
     // Write a byte if StartAddress is byte aligned\r
     //\r
     //\r
     // Write a byte if StartAddress is byte aligned\r
     //\r

-    PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+    PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r

     StartAddress += sizeof (UINT8);\r
     StartAddress += sizeof (UINT8);\r

-    Size -= sizeof (UINT8);\r
-    Buffer = (UINT8*)Buffer + 1;\r
+    Size         -= sizeof (UINT8);\r
+    Buffer        = (UINT8 *)Buffer + 1;\r

   }\r
 \r
   }\r
 \r

-  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+  if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r

     //\r
     // Write a word if StartAddress is word aligned\r
     //\r
     PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
     StartAddress += sizeof (UINT16);\r
     //\r
     // Write a word if StartAddress is word aligned\r
     //\r
     PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
     StartAddress += sizeof (UINT16);\r

-    Size -= sizeof (UINT16);\r
-    Buffer = (UINT16*)Buffer + 1;\r
+    Size         -= sizeof (UINT16);\r
+    Buffer        = (UINT16 *)Buffer + 1;\r

   }\r
 \r
   while (Size >= sizeof (UINT32)) {\r
   }\r
 \r
   while (Size >= sizeof (UINT32)) {\r


@@ -1394,8 +1401,8 @@ PciWriteBuffer (
     //\r
     PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
     StartAddress += sizeof (UINT32);\r
     //\r
     PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
     StartAddress += sizeof (UINT32);\r

-    Size -= sizeof (UINT32);\r
-    Buffer = (UINT32*)Buffer + 1;\r
+    Size         -= sizeof (UINT32);\r
+    Buffer        = (UINT32 *)Buffer + 1;\r

   }\r
 \r
   if (Size >= sizeof (UINT16)) {\r
   }\r
 \r
   if (Size >= sizeof (UINT16)) {\r


@@ -1404,15 +1411,15 @@ PciWriteBuffer (
     //\r
     PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
     StartAddress += sizeof (UINT16);\r
     //\r
     PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
     StartAddress += sizeof (UINT16);\r

-    Size -= sizeof (UINT16);\r
-    Buffer = (UINT16*)Buffer + 1;\r
+    Size         -= sizeof (UINT16);\r
+    Buffer        = (UINT16 *)Buffer + 1;\r

   }\r
 \r
   if (Size >= sizeof (UINT8)) {\r
     //\r
     // Write the last remaining byte if exist\r
     //\r
   }\r
 \r
   if (Size >= sizeof (UINT8)) {\r
     //\r
     // Write the last remaining byte if exist\r
     //\r

-    PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+    PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r

   }\r
 \r
   return ReturnValue;\r
   }\r
 \r
   return ReturnValue;\r