-#define __DECL_REG(n64, n32) UINT64 n64\r
-#endif\r
-\r
-struct vcpu_guest_core_regs\r
-{\r
- /* Aarch64 Aarch32 */\r
- __DECL_REG(x0, r0_usr);\r
- __DECL_REG(x1, r1_usr);\r
- __DECL_REG(x2, r2_usr);\r
- __DECL_REG(x3, r3_usr);\r
- __DECL_REG(x4, r4_usr);\r
- __DECL_REG(x5, r5_usr);\r
- __DECL_REG(x6, r6_usr);\r
- __DECL_REG(x7, r7_usr);\r
- __DECL_REG(x8, r8_usr);\r
- __DECL_REG(x9, r9_usr);\r
- __DECL_REG(x10, r10_usr);\r
- __DECL_REG(x11, r11_usr);\r
- __DECL_REG(x12, r12_usr);\r
-\r
- __DECL_REG(x13, sp_usr);\r
- __DECL_REG(x14, lr_usr);\r
-\r
- __DECL_REG(x15, __unused_sp_hyp);\r
-\r
- __DECL_REG(x16, lr_irq);\r
- __DECL_REG(x17, sp_irq);\r
-\r
- __DECL_REG(x18, lr_svc);\r
- __DECL_REG(x19, sp_svc);\r
-\r
- __DECL_REG(x20, lr_abt);\r
- __DECL_REG(x21, sp_abt);\r
-\r
- __DECL_REG(x22, lr_und);\r
- __DECL_REG(x23, sp_und);\r
-\r
- __DECL_REG(x24, r8_fiq);\r
- __DECL_REG(x25, r9_fiq);\r
- __DECL_REG(x26, r10_fiq);\r
- __DECL_REG(x27, r11_fiq);\r
- __DECL_REG(x28, r12_fiq);\r
-\r
- __DECL_REG(x29, sp_fiq);\r
- __DECL_REG(x30, lr_fiq);\r
-\r
- /* Return address and mode */\r
- __DECL_REG(pc64, pc32); /* ELR_EL2 */\r
- UINT32 cpsr; /* SPSR_EL2 */\r
-\r
- union {\r
- UINT32 spsr_el1; /* AArch64 */\r
- UINT32 spsr_svc; /* AArch32 */\r
- };\r
-\r
- /* AArch32 guests only */\r
- UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt;\r
-\r
- /* AArch64 guests only */\r
- UINT64 sp_el0;\r
- UINT64 sp_el1, elr_el1;\r
+#define __DECL_REG(n64, n32) UINT64 n64\r
+ #endif\r
+\r
+struct vcpu_guest_core_regs {\r
+ /* Aarch64 Aarch32 */\r
+ __DECL_REG (x0, r0_usr);\r
+ __DECL_REG (x1, r1_usr);\r
+ __DECL_REG (x2, r2_usr);\r
+ __DECL_REG (x3, r3_usr);\r
+ __DECL_REG (x4, r4_usr);\r
+ __DECL_REG (x5, r5_usr);\r
+ __DECL_REG (x6, r6_usr);\r
+ __DECL_REG (x7, r7_usr);\r
+ __DECL_REG (x8, r8_usr);\r
+ __DECL_REG (x9, r9_usr);\r
+ __DECL_REG (x10, r10_usr);\r
+ __DECL_REG (x11, r11_usr);\r
+ __DECL_REG (x12, r12_usr);\r
+\r
+ __DECL_REG (x13, sp_usr);\r
+ __DECL_REG (x14, lr_usr);\r
+\r
+ __DECL_REG (x15, __unused_sp_hyp);\r
+\r
+ __DECL_REG (x16, lr_irq);\r
+ __DECL_REG (x17, sp_irq);\r
+\r
+ __DECL_REG (x18, lr_svc);\r
+ __DECL_REG (x19, sp_svc);\r
+\r
+ __DECL_REG (x20, lr_abt);\r
+ __DECL_REG (x21, sp_abt);\r
+\r
+ __DECL_REG (x22, lr_und);\r
+ __DECL_REG (x23, sp_und);\r
+\r
+ __DECL_REG (x24, r8_fiq);\r
+ __DECL_REG (x25, r9_fiq);\r
+ __DECL_REG (x26, r10_fiq);\r
+ __DECL_REG (x27, r11_fiq);\r
+ __DECL_REG (x28, r12_fiq);\r
+\r
+ __DECL_REG (x29, sp_fiq);\r
+ __DECL_REG (x30, lr_fiq);\r
+\r
+ /* Return address and mode */\r
+ __DECL_REG (pc64, pc32); /* ELR_EL2 */\r
+ UINT32 cpsr; /* SPSR_EL2 */\r
+\r
+ union {\r
+ UINT32 spsr_el1; /* AArch64 */\r
+ UINT32 spsr_svc; /* AArch32 */\r
+ };\r
+\r
+ /* AArch32 guests only */\r
+ UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt;\r
+\r
+ /* AArch64 guests only */\r
+ UINT64 sp_el0;\r
+ UINT64 sp_el1, elr_el1;\r