- PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (\r
- ProcessorNumber,\r
- Msr,\r
- MSR_IA32_APIC_BASE,\r
- MSR_IA32_APIC_BASE_REGISTER,\r
- Bits.EXTD,\r
- (State) ? 1 : 0\r
- );\r
+ BOOLEAN *X2ApicEnabled;\r
+\r
+ ASSERT (ConfigData != NULL);\r
+ X2ApicEnabled = (BOOLEAN *) ConfigData;\r
+ if (X2ApicEnabled[ProcessorNumber]) {\r
+ PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (\r
+ ProcessorNumber,\r
+ Msr,\r
+ MSR_IA32_APIC_BASE,\r
+ MSR_IA32_APIC_BASE_REGISTER,\r
+ Bits.EXTD,\r
+ 1\r
+ );\r
+ } else {\r
+ //\r
+ // Enable X2APIC mode only if X2APIC is not enabled,\r
+ // Needn't to disabe X2APIC mode again if X2APIC is not enabled\r
+ //\r
+ if (State) {\r
+ CPU_REGISTER_TABLE_WRITE_FIELD (\r
+ ProcessorNumber,\r
+ Msr,\r
+ MSR_IA32_APIC_BASE,\r
+ MSR_IA32_APIC_BASE_REGISTER,\r
+ Bits.EXTD,\r
+ 1\r
+ );\r
+ }\r
+ }\r