-/**\r
- Perform SMM initialization for all processors in the S3 boot path.\r
-\r
- For a native platform, MP initialization in the S3 boot path is also performed in this function.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmRestoreCpu (\r
- VOID\r
- )\r
-{\r
- SMM_S3_RESUME_STATE *SmmS3ResumeState;\r
- IA32_DESCRIPTOR Ia32Idtr;\r
- IA32_DESCRIPTOR X64Idtr;\r
- IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];\r
- EFI_STATUS Status;\r
-\r
- DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));\r
-\r
- //\r
- // See if there is enough context to resume PEI Phase\r
- //\r
- if (mSmmS3ResumeState == NULL) {\r
- DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));\r
- CpuDeadLoop ();\r
- }\r
-\r
- SmmS3ResumeState = mSmmS3ResumeState;\r
- ASSERT (SmmS3ResumeState != NULL);\r
-\r
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
- //\r
- // Save the IA32 IDT Descriptor\r
- //\r
- AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
-\r
- //\r
- // Setup X64 IDT table\r
- //\r
- ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);\r
- X64Idtr.Base = (UINTN) IdtEntryTable;\r
- X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);\r
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);\r
-\r
- //\r
- // Setup the default exception handler\r
- //\r
- Status = InitializeCpuExceptionHandlers (NULL);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Initialize Debug Agent to support source level debug\r
- //\r
- InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);\r
- }\r
-\r
- //\r
- // Skip initialization if mAcpiCpuData is not valid\r
- //\r
- if (mAcpiCpuData.NumberOfCpus > 0) {\r
- //\r
- // First time microcode load and restore MTRRs\r
- //\r
- EarlyInitializeCpu ();\r
- }\r
-\r
- //\r
- // Restore SMBASE for BSP and all APs\r
- //\r
- SmmRelocateBases ();\r
-\r
- //\r
- // Skip initialization if mAcpiCpuData is not valid\r
- //\r
- if (mAcpiCpuData.NumberOfCpus > 0) {\r
- //\r
- // Restore MSRs for BSP and all APs\r
- //\r
- InitializeCpu ();\r
- }\r
-\r
- //\r
- // Set a flag to restore SMM configuration in S3 path.\r
- //\r
- mRestoreSmmConfigurationInS3 = TRUE;\r
-\r
- DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));\r
- DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
- DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));\r
- DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));\r
- DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
-\r
- //\r
- // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase\r
- //\r
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {\r
- DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));\r
-\r
- SwitchStack (\r
- (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,\r
- (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,\r
- (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,\r
- (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer\r
- );\r
- }\r
-\r
- //\r
- // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase\r
- //\r
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
- DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));\r
- //\r
- // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.\r
- //\r
- SaveAndSetDebugTimerInterrupt (FALSE);\r
- //\r
- // Restore IA32 IDT table\r
- //\r
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
- AsmDisablePaging64 (\r
- SmmS3ResumeState->ReturnCs,\r
- (UINT32)SmmS3ResumeState->ReturnEntryPoint,\r
- (UINT32)SmmS3ResumeState->ReturnContext1,\r
- (UINT32)SmmS3ResumeState->ReturnContext2,\r
- (UINT32)SmmS3ResumeState->ReturnStackPointer\r
- );\r
- }\r
-\r
- //\r
- // Can not resume PEI Phase\r
- //\r
- DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));\r
- CpuDeadLoop ();\r
-}\r
-\r
-/**\r
- Copy register table from ACPI NVS memory into SMRAM.\r
-\r
- @param[in] DestinationRegisterTableList Points to destination register table.\r
- @param[in] SourceRegisterTableList Points to source register table.\r
- @param[in] NumberOfCpus Number of CPUs.\r
-\r
-**/\r
-VOID\r
-CopyRegisterTable (\r
- IN CPU_REGISTER_TABLE *DestinationRegisterTableList,\r
- IN CPU_REGISTER_TABLE *SourceRegisterTableList,\r
- IN UINT32 NumberOfCpus\r
- )\r
-{\r
- UINTN Index;\r
- UINTN Index1;\r
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;\r
-\r
- CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
- for (Index = 0; Index < NumberOfCpus; Index++) {\r
- DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
- ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);\r
- CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
- //\r
- // Go though all MSRs in register table to initialize MSR spin lock\r
- //\r
- RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;\r
- for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
- if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
- //\r
- // Initialize MSR spin lock only for those MSRs need bit field writing\r
- //\r
- InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
- }\r
- }\r
- }\r
-}\r
-\r