# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
Include # Root include for the package\r
\r
[LibraryClasses.common]\r
- ArmLib|Include/Library/ArmLib.h\r
- ArmMmuLib|Include/Library/ArmMmuLib.h\r
- SemihostLib|Include/Library/Semihosting.h\r
- DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
+ ## @libraryclass Convert Arm instructions to a human readable format.\r
+ #\r
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
+\r
+ ## @libraryclass Provides an interface to Arm generic counters.\r
+ #\r
+ ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h\r
+\r
+ ## @libraryclass Provides an interface to initialize a\r
+ # Generic Interrupt Controller (GIC).\r
+ #\r
ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
- ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r
+\r
+ ## @libraryclass Provides a Generic Interrupt Controller (GIC)\r
+ # configuration interface.\r
+ #\r
+ ArmGicLib|Include/Library/ArmGicLib.h\r
+\r
+ ## @libraryclass Provides a HyperVisor Call (HVC) interface.\r
+ #\r
+ ArmHvcLib|Include/Library/ArmHvcLib.h\r
+\r
+ ## @libraryclass Provides an interface to Arm registers.\r
+ #\r
+ ArmLib|Include/Library/ArmLib.h\r
+\r
+ ## @libraryclass Provides a Mmu interface.\r
+ #\r
+ ArmMmuLib|Include/Library/ArmMmuLib.h\r
+\r
+ ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface\r
+ # for the System Control and Management Interface (SCMI).\r
+ #\r
+ ArmMtlLib|Include/Library/ArmMtlLib.h\r
+\r
+ ## @libraryclass Provides a System Monitor Call (SMC) interface.\r
+ #\r
+ ArmSmcLib|Include/Library/ArmSmcLib.h\r
+\r
+ ## @libraryclass Provides a SuperVisor Call (SVC) interface.\r
+ #\r
ArmSvcLib|Include/Library/ArmSvcLib.h\r
+\r
+ ## @libraryclass Provides a default exception handler.\r
+ #\r
+ DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
+\r
+ ## @libraryclass Provides an interface to query miscellaneous OEM\r
+ # information.\r
+ #\r
+ OemMiscLib|Include/Library/OemMiscLib.h\r
+\r
+ ## @libraryclass Provides an OpTee interface.\r
+ #\r
OpteeLib|Include/Library/OpteeLib.h\r
+\r
+ ## @libraryclass Provides a semihosting interface.\r
+ #\r
+ SemihostLib|Include/Library/SemihostLib.h\r
+\r
+ ## @libraryclass Provides an interface for a StandaloneMm Mmu.\r
+ #\r
StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r
\r
[Guids.common]\r
# Define if the GICv3 controller should use the GICv2 legacy\r
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
- # Whether to implement warm reboot for capsule update using a jump back to the\r
- # PEI entry point with caches and interrupts disabled.\r
- gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F\r
-\r
[PcdsFeatureFlag.ARM]\r
# Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
# TRUE may be appropriate to fix performance problems if you don't care about\r
# hardware coherency (i.e., no virtualization or cache coherent DMA)\r
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
\r
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]\r
+ ## Used to select method for requesting services from S-EL1.<BR><BR>\r
+ # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r
+ # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r
+ # @Prompt Enable FF-A support.\r
+ gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r
+\r
[PcdsFixedAtBuild.common]\r
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
\r
# The Primary Core is ClusterId[0] & CoreId[0]\r
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
+ #\r
+ # SMBIOS PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r
+ gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r
+ gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r
+ gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r
+ gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r
+ gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r
+ gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r
+ gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r
+ gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r
+ gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r
+\r
#\r
# ARM L2x0 PCDs\r
#\r
gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r
gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r
\r
+ gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r
+ gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r
+\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
#\r
# ARM Architectural Timer\r
# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
#\r
- # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
- # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
- # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
#\r
# because (a) the target address space (ie. the cpu-physical space) is\r
# 64-bit, and (b) the translation values are meant as offsets for *modular*\r
# UINT64 TranslatedMmio64Address; // output parameter\r
#\r
# TranslatedIoAddress = UntranslatedIoAddress +\r
- # PcdPciIoTranslation;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;\r
# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
- # PcdPciMmio32Translation;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;\r
# TranslatedMmio64Address = UntranslatedMmio64Address +\r
- # PcdPciMmio64Translation;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;\r
#\r
# The modular arithmetic performed in UINT64 ensures that the translation\r
# works correctly regardless of the relation between IoCpuBase and\r
#\r
gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
- gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
- gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
- gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
\r
#\r
# Inclusive range of allowed PCI buses.\r
#\r
gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r
+\r
+[PcdsDynamicEx]\r
+ #\r
+ # This dynamic PCD hold the GUID of a firmware FFS which contains\r
+ # the LinuxBoot payload.\r
+ #\r
+ gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C\r