\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
-Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR> \r
+Portions copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
- Gic.c\r
+ ArmGicDxe.c\r
\r
Abstract:\r
\r
\r
#include <PiDxe.h>\r
\r
-#include <Library/ArmLib.h>\r
#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
-#include <Protocol/Cpu.h>\r
-#include <Protocol/HardwareInterrupt.h>\r
+#include "ArmGicDxe.h"\r
\r
#define ARM_GIC_DEFAULT_PRIORITY 0x80\r
\r
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r
\r
-//\r
-// Notifications\r
-//\r
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
-\r
-// Maximum Number of Interrupts\r
-UINTN mGicNumInterrupts = 0;\r
-\r
-HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;\r
-\r
-/**\r
- Register Handler for the specified interrupt source.\r
-\r
- @param This Instance pointer for this protocol\r
- @param Source Hardware source of the interrupt\r
- @param Handler Callback for interrupt. NULL to unregister\r
-\r
- @retval EFI_SUCCESS Source was updated to support Handler.\r
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RegisterInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN HARDWARE_INTERRUPT_HANDLER Handler\r
- )\r
-{\r
- if (Source > mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
- \r
- if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
- return EFI_ALREADY_STARTED;\r
- }\r
-\r
- gRegisteredInterruptHandlers[Source] = Handler;\r
-\r
- // If the interrupt handler is unregistered then disable the interrupt\r
- if (NULL == Handler){\r
- return This->DisableInterruptSource (This, Source);\r
- } else {\r
- return This->EnableInterruptSource (This, Source);\r
- }\r
-}\r
-\r
/**\r
Enable interrupt source Source.\r
\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- \r
if (Source > mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
- // Calculate enable register offset and bit position\r
- RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
\r
- // Write set-enable register\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);\r
- \r
+ ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- \r
if (Source > mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
- // Calculate enable register offset and bit position\r
- RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
\r
- // Write set-enable register\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);\r
- \r
+ ArmGicDisableInterrupt (PcdGet32(PcdGicDistributorBase), Source);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
IN BOOLEAN *InterruptState\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- \r
if (Source > mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
- // calculate enable register offset and bit position\r
- RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
- \r
- if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {\r
- *InterruptState = FALSE;\r
- } else {\r
- *InterruptState = TRUE;\r
- }\r
- \r
+\r
+ *InterruptState = ArmGicIsInterruptEnabled (PcdGet32(PcdGicDistributorBase), Source);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
UINT32 GicInterrupt;\r
HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
\r
- GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);\r
+ GicInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicInterruptInterfaceBase));\r
\r
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
- if (GicInterrupt >= mGicNumInterrupts) {\r
+ if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
// The special interrupt do not need to be acknowledge\r
return;\r
}\r
EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r
}\r
\r
-//\r
-// Making this global saves a few bytes in image size\r
-//\r
-EFI_HANDLE gHardwareInterruptHandle = NULL;\r
-\r
//\r
// The protocol instance produced by this driver\r
//\r
}\r
\r
// Disable Gic Interface\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);\r
+ ArmGicDisableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
\r
// Disable Gic Distributor\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);\r
+ ArmGicDisableDistributor (PcdGet32(PcdGicDistributorBase));\r
}\r
\r
/**\r
UINTN Index;\r
UINT32 RegOffset;\r
UINTN RegShift;\r
- EFI_CPU_ARCH_PROTOCOL *Cpu;\r
UINT32 CpuTarget;\r
\r
// Make sure the Interrupt Controller Protocol is not already installed in the system.\r
\r
// Set priority mask reg to 0xff to allow all priorities through\r
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r
- \r
+\r
// Enable gic cpu interface\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);\r
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
\r
// Enable gic distributor\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);\r
- \r
- // Initialize the array for the Interrupt Handlers\r
- gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
- \r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &gHardwareInterruptHandle,\r
- &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- \r
- //\r
- // Get the CPU protocol that this driver requires.\r
- //\r
- Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- //\r
- // Unregister the default exception handler.\r
- //\r
- Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- //\r
- // Register to receive interrupts\r
- //\r
- Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler);\r
- ASSERT_EFI_ERROR(Status);\r
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
\r
- // Register for an ExitBootServicesEvent\r
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
- ASSERT_EFI_ERROR (Status);\r
+ Status = InstallAndRegisterInterruptService (\r
+ &gHardwareInterruptProtocol, IrqInterruptHandler, ExitBootServicesEvent);\r
\r
return Status;\r
}\r
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