/** @file\r
*\r
-* Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2021, Arm Limited. All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
+ ARM_GICR_SGI_VLPI_FRAME_SIZE \\r
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)\r
\r
-#define ISENABLER_ADDRESS(base,offset) ((base) + \\r
- ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))\r
+#define ISENABLER_ADDRESS(base, offset) ((base) +\\r
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))\r
\r
-#define ICENABLER_ADDRESS(base,offset) ((base) + \\r
- ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset))\r
+#define ICENABLER_ADDRESS(base, offset) ((base) +\\r
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))\r
+\r
+#define IPRIORITY_ADDRESS(base, offset) ((base) +\\r
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))\r
\r
/**\r
*\r
STATIC\r
UINTN\r
GicGetCpuRedistributorBase (\r
- IN UINTN GicRedistributorBase,\r
- IN ARM_GIC_ARCH_REVISION Revision\r
+ IN UINTN GicRedistributorBase,\r
+ IN ARM_GIC_ARCH_REVISION Revision\r
)\r
{\r
- UINTN MpId;\r
- UINTN CpuAffinity;\r
- UINTN Affinity;\r
- UINTN GicCpuRedistributorBase;\r
- UINT64 TypeRegister;\r
+ UINTN MpId;\r
+ UINTN CpuAffinity;\r
+ UINTN Affinity;\r
+ UINTN GicCpuRedistributorBase;\r
+ UINT64 TypeRegister;\r
\r
MpId = ArmReadMpidr ();\r
// Define CPU affinity as:\r
\r
do {\r
TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);\r
- Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);\r
+ Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);\r
if (Affinity == CpuAffinity) {\r
return GicCpuRedistributorBase;\r
}\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
// Read the GIC Identification Register\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
)\r
{\r
- return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
+ UINTN ItLines;\r
+\r
+ ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;\r
+\r
+ //\r
+ // Interrupt ID 1020-1023 are reserved.\r
+ //\r
+ return (ItLines == 0x1f) ? 1020 : 32 * (ItLines + 1);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList,\r
- IN INTN SgiId\r
+ IN INTN GicDistributorBase,\r
+ IN INTN TargetListFilter,\r
+ IN INTN CPUTargetList,\r
+ IN INTN SgiId\r
)\r
{\r
MmioWrite32 (\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *InterruptId\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *InterruptId\r
)\r
{\r
- UINTN Value;\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN Value;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- IN UINTN Source\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicSetInterruptPriority (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source,\r
- IN UINTN Priority\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source,\r
+ IN UINTN Priority\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
\r
// Calculate register offset and bit position\r
RegOffset = Source / 4;\r
- RegShift = (Source % 4) * 8;\r
+ RegShift = (Source % 4) * 8;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
MmioAndThenOr32 (\r
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
~(0xff << RegShift),\r
}\r
\r
MmioAndThenOr32 (\r
- GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
+ IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),\r
~(0xff << RegShift),\r
Priority << RegShift\r
);\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
\r
// Calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
+ RegShift = Source % 32;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
// Write set-enable register\r
MmioWrite32 (\r
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),\r
\r
// Write set-enable register\r
MmioWrite32 (\r
- ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),\r
+ ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),\r
1 << RegShift\r
);\r
}\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
\r
// Calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
+ RegShift = Source % 32;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
// Write clear-enable register\r
MmioWrite32 (\r
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),\r
);\r
} else {\r
GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
- GicRedistributorBase,\r
- Revision\r
- );\r
+ GicRedistributorBase,\r
+ Revision\r
+ );\r
if (GicCpuRedistributorBase == 0) {\r
return;\r
}\r
\r
// Write clear-enable register\r
MmioWrite32 (\r
- ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),\r
+ ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),\r
1 << RegShift\r
);\r
}\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
- UINT32 Interrupts;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
+ UINT32 Interrupts;\r
\r
// Calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
+ RegShift = Source % 32;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
Interrupts = ((MmioRead32 (\r
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)\r
)\r
- & (1 << RegShift)) != 0);\r
+ & (1 << RegShift)) != 0);\r
} else {\r
GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
GicRedistributorBase,\r
\r
// Read set-enable register\r
Interrupts = MmioRead32 (\r
- ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)\r
+ ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)\r
);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
)\r
{\r
// Disable Gic Distributor\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r