ArmPkg/ArmGicLib: use correct loop variable

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / ArmGicLib.c

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 48708e3812b4736fcd2399e05a92cab02f532555..e658e9bff5d8107b3914bdf1e9e1e51a4e4d4cd7 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -19,8 +19,18 @@
 #include <Library/IoLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
-#include "GicV2/ArmGicV2Lib.h"\r
-#include "GicV3/ArmGicV3Lib.h"\r
+/**\r
+ *\r
+ * Return whether the Source interrupt index refers to a shared interrupt (SPI)\r
+ */\r
+STATIC\r
+BOOLEAN\r
+SourceIsSpi (\r
+  IN UINTN  Source\r
+  )\r
+{\r
+  return Source >= 32 && Source < 1020;\r
+}\r
 \r
 /**\r
  * Return the base address of the GIC redistributor for the current CPU\r
@@ -66,7 +76,7 @@ GicGetCpuRedistributorBase (
     }\r
 \r
     // Move to the next GIC Redistributor frame\r
-    GicRedistributorBase += GicRedistributorGranularity;\r
+    GicCpuRedistributorBase += GicRedistributorGranularity;\r
   }\r
 \r
   // The Redistributor has not been found for the current CPU\r
@@ -186,7 +196,9 @@ ArmGicEnableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
+      SourceIsSpi (Source)) {\r
     // Write set-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -219,7 +231,9 @@ ArmGicDisableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
+      SourceIsSpi (Source)) {\r
     // Write clear-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -252,7 +266,9 @@ ArmGicIsInterruptEnabled (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
+      SourceIsSpi (Source)) {\r
     Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
   } else {\r
     GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r