IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
-\r
if (ExceptionType <= MAX_ARM_EXCEPTION) {\r
if (gExceptionHandlers[ExceptionType]) {\r
gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);\r
UINT32 *VectorBase;\r
\r
Status = EFI_SUCCESS;\r
+ ZeroMem (gExceptionHandlers,sizeof(*gExceptionHandlers));\r
+\r
//\r
// Disable interrupts\r
//\r
//\r
Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;\r
\r
+ // Check if the exception vector is in the low address\r
+ if (PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) {\r
+ // Set SCTLR.V to 0 to enable VBAR to be used\r
+ ArmSetLowVectors ();\r
+ } else {\r
+ ArmSetHighVectors ();\r
+ }\r
+\r
//\r
// Reserve space for the exception handlers\r
//\r
\r
//Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.\r
// The Vector Base Address Register defines the location\r
- ArmWriteVBar(PcdGet32(PcdCpuVectorBaseAddress));\r
+ ArmWriteVBar (PcdGet32(PcdCpuVectorBaseAddress));\r
} else {\r
+ // The Vector table must be 32-byte aligned\r
+ ASSERT(((UINT32)ExceptionHandlersStart & ((1 << 5)-1)) == 0);\r
+\r
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.\r
- ArmWriteVBar((UINT32)ExceptionHandlersStart);\r
+ ArmWriteVBar ((UINT32)ExceptionHandlersStart);\r
}\r
\r
if (FiqEnabled) {\r