OvmfPkg/Virtio.h: Added the Virtio Vendor and MMIO IDs

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicNonSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
index 526af02d3ee23caa829f99545eff9beeea7dbf05..55ff56e7974fe1154b12589761ad78ae2aac1da7 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
@@ -12,86 +12,33 @@
 *\r
 **/\r
 \r
+#include <Uefi.h>\r
 #include <Library/IoLib.h>\r
-#include <Drivers/PL390Gic.h>\r
+#include <Library/ArmGicLib.h>\r
 \r
 \r
 VOID\r
 EFIAPI\r
-PL390GicEnableInterruptInterface (\r
+ArmGicEnableInterruptInterface (\r
   IN  INTN          GicInterruptInterfaceBase\r
   )\r
 {  \r
   /*\r
-   * Enable the CPU interface in Non-Secure world\r
-   * Note: The ICCICR register is banked when Security extensions are implemented   \r
-   */\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
+  * Enable the CPU interface in Non-Secure world\r
+  * Note: The ICCICR register is banked when Security extensions are implemented\r
+  */\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
 }\r
 \r
 VOID\r
 EFIAPI\r
-PL390GicEnableDistributor (\r
+ArmGicEnableDistributor (\r
   IN  INTN          GicDistributorBase\r
   )\r
 {\r
-    /*\r
-     * Enable GIC distributor in Non-Secure world.\r
-     * Note: The ICDDCR register is banked when Security extensions are implemented\r
-     */\r
-    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-PL390GicSendSgiTo (\r
-  IN  INTN          GicDistributorBase,\r
-  IN  INTN          TargetListFilter,\r
-  IN  INTN          CPUTargetList\r
-  )\r
-{\r
-  MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
-}\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgiFrom (\r
-  IN  INTN          GicInterruptInterfaceBase,\r
-  IN  INTN          CoreId\r
-  )\r
-{\r
-    INTN            InterruptId;\r
-\r
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
-  if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-        return 1;\r
-    } else {\r
-        return 0;\r
-    }\r
-}\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgi2From (\r
-  IN  INTN          GicInterruptInterfaceBase,\r
-  IN  INTN          CoreId,\r
-  IN  INTN          SgiId\r
-  )\r
-{\r
-    INTN            InterruptId;\r
-\r
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
-  if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-        return 1;\r
-    } else {\r
-        return 0;\r
-    }\r
+  /*\r
+   * Enable GIC distributor in Non-Secure world.\r
+   * Note: The ICDDCR register is banked when Security extensions are implemented\r
+   */\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);\r
 }\r