/** @file\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
**/\r
\r
#include <Base.h>\r
+#include <Library/ArmLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
+ IN UINTN MpId,\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
)\r
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
}\r
\r
- // Ensure all GIC interrupts are Non-Secure\r
- for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
+ // Ensure all GIC interrupts are Non-Secure\r
+ for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ }\r
+ } else {\r
+ // The secondary cores only set the Non Secure bit to their banked PPIs\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
}\r
\r
// Ensure all interrupts can get through the priority mask\r