ArmPkg/PL390Gic: Do not try to clear spurious interrupts.

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index c137c95f20587951a850ce280b20ead406ca4b08..6244575772bf67d25d15e7f1afa1c9dc1321a537 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -39,14 +39,15 @@ ArmGicSetupNonSecure (
   // Set priority Mask so that no interrupts get through to CPU\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
 \r
-  // Check if there are any pending interrupts\r
-  //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
-  while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
-    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+  InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
 \r
-    // Write to End of interrupt signal\r
+  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+  while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase))   {\r
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
     MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+\r
+    // Next\r
+    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
   }\r
 \r
   // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
@@ -99,7 +100,7 @@ ArmGicEnableInterruptInterface (
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
 \r
   // Enable CPU interface in Secure world\r
-  // Enable CPU inteface in Non-secure World\r
+  // Enable CPU interface in Non-secure World\r
   // Signal Secure Interrupts to CPU using FIQ line *\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
       ARM_GIC_ICCICR_ENABLE_SECURE |\r
@@ -107,6 +108,19 @@ ArmGicEnableInterruptInterface (
       ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
 }\r
 \r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  UINT32    ControlValue;\r
+\r
+  // Disable CPU interface in Secure world and Non-secure World\r
+  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
+}\r
+\r
 VOID\r
 EFIAPI\r
 ArmGicEnableDistributor (\r