#define ARM_CPU_TYPE_AEMv8 0xD0F\r
#define ARM_CPU_TYPE_A53 0xD03\r
#define ARM_CPU_TYPE_A57 0xD07\r
+#define ARM_CPU_TYPE_A72 0xD08\r
#define ARM_CPU_TYPE_A15 0xC0F\r
#define ARM_CPU_TYPE_A9 0xC09\r
#define ARM_CPU_TYPE_A7 0xC07\r
\r
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r
\r
+// Vector table offset definitions\r
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000\r
+#define ARM_VECTOR_CUR_SP0_IRQ 0x080\r
+#define ARM_VECTOR_CUR_SP0_FIQ 0x100\r
+#define ARM_VECTOR_CUR_SP0_SERR 0x180\r
+\r
+#define ARM_VECTOR_CUR_SPx_SYNC 0x200\r
+#define ARM_VECTOR_CUR_SPx_IRQ 0x280\r
+#define ARM_VECTOR_CUR_SPx_FIQ 0x300\r
+#define ARM_VECTOR_CUR_SPx_SERR 0x380\r
+\r
+#define ARM_VECTOR_LOW_A64_SYNC 0x400\r
+#define ARM_VECTOR_LOW_A64_IRQ 0x480\r
+#define ARM_VECTOR_LOW_A64_FIQ 0x500\r
+#define ARM_VECTOR_LOW_A64_SERR 0x580\r
+\r
+#define ARM_VECTOR_LOW_A32_SYNC 0x600\r
+#define ARM_VECTOR_LOW_A32_IRQ 0x680\r
+#define ARM_VECTOR_LOW_A32_FIQ 0x700\r
+#define ARM_VECTOR_LOW_A32_SERR 0x780\r
+\r
+#define VECTOR_BASE(tbl) \\r
+ .section .text.##tbl##,"ax"; \\r
+ .align 11; \\r
+ .org 0x0; \\r
+ GCC_ASM_EXPORT(tbl); \\r
+ ASM_PFX(tbl): \\r
+\r
+#define VECTOR_ENTRY(tbl, off) \\r
+ .org off\r
+\r
+#define VECTOR_END(tbl) \\r
+ .org 0x800; \\r
+ .previous\r
+\r
VOID\r
EFIAPI\r
ArmEnableSWPInstruction (\r
IN UINTN Hcr\r
);\r
\r
+UINTN\r
+ArmReadHcr (\r
+ VOID\r
+ );\r
+\r
UINTN\r
ArmReadCurrentEL (\r
VOID\r