*\r
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))\r
\r
-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1 << TT_ADDRESS_OFFSET_AT_LEVEL(Level))\r
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))\r
\r
// Get the associated entry in the given Translation Table\r
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \\r
- ((UINTN)(TranslationTable) + ((((Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))\r
+ ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))\r
\r
// Return the smallest address granularity from the table level.\r
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r
-#define TT_ADDRESS_AT_LEVEL(TableLevel) (1 << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))\r
+#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))\r
+\r
+#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \\r
+ ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))\r
\r
// There are 512 entries per table when 4K Granularity\r
#define TT_ENTRY_COUNT 512\r
#define TT_ALIGNMENT_BLOCK_ENTRY BIT12\r
#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12\r
\r
-#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFULL << 12)\r
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFULL << 12)\r
+#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)\r
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)\r
\r
#define TT_TYPE_MASK 0x3\r
#define TT_TYPE_TABLE_ENTRY 0x3\r
#define TT_NS BIT5\r
#define TT_AF BIT10\r
\r
+#define TT_SH_NON_SHAREABLE (0x0 << 8)\r
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)\r
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)\r
+#define TT_SH_MASK (0x3 << 8)\r
+\r
#define TT_PXN_MASK BIT53\r
-#define TT_UXN_MASK BIT54\r
+#define TT_UXN_MASK BIT54 // EL1&0\r
+#define TT_XN_MASK BIT54 // EL2 / EL3\r
\r
#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))\r
\r
#define TT_TABLE_PXN BIT59\r
-#define TT_TABLE_XN BIT60\r
+#define TT_TABLE_UXN BIT60 // EL1&0\r
+#define TT_TABLE_XN BIT60 // EL2 / EL3\r
#define TT_TABLE_NS BIT63\r
\r
#define TT_TABLE_AP_MASK (BIT62 | BIT61)\r
//\r
// Translation Control Register\r
//\r
-#define TCR_T0SZ_MASK 0x3F\r
+#define TCR_T0SZ_MASK 0x3FUL\r
\r
-#define TCR_PS_4GB (0 << 16)\r
-#define TCR_PS_64GB (1 << 16)\r
-#define TCR_PS_1TB (2 << 16)\r
-#define TCR_PS_4TB (3 << 16)\r
-#define TCR_PS_16TB (4 << 16)\r
-#define TCR_PS_256TB (5 << 16)\r
+#define TCR_PS_4GB (0UL << 16)\r
+#define TCR_PS_64GB (1UL << 16)\r
+#define TCR_PS_1TB (2UL << 16)\r
+#define TCR_PS_4TB (3UL << 16)\r
+#define TCR_PS_16TB (4UL << 16)\r
+#define TCR_PS_256TB (5UL << 16)\r
\r
-#define TCR_TG0_4KB (0 << 14)\r
+#define TCR_TG0_4KB (0UL << 14)\r
+#define TCR_TG1_4KB (2UL << 30)\r
\r
-#define TCR_IPS_4GB (0UL << 32)\r
-#define TCR_IPS_64GB (1UL << 32)\r
-#define TCR_IPS_1TB (2UL << 32)\r
-#define TCR_IPS_4TB (3UL << 32)\r
-#define TCR_IPS_16TB (4UL << 32)\r
-#define TCR_IPS_256TB (5UL << 32)\r
+#define TCR_IPS_4GB (0ULL << 32)\r
+#define TCR_IPS_64GB (1ULL << 32)\r
+#define TCR_IPS_1TB (2ULL << 32)\r
+#define TCR_IPS_4TB (3ULL << 32)\r
+#define TCR_IPS_16TB (4ULL << 32)\r
+#define TCR_IPS_256TB (5ULL << 32)\r
\r
+#define TCR_EPD1 (1UL << 23)\r
\r
#define TTBR_ASID_FIELD (48)\r
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)\r
#define TCR_EL1_AS_FIELD (36)\r
#define TCR_EL1_TBI0_FIELD (37)\r
#define TCR_EL1_TBI1_FIELD (38)\r
-#define TCR_EL1_T0SZ_MASK (0x1F << TCR_EL1_T0SZ_FIELD)\r
-#define TCR_EL1_EPD0_MASK (0x1 << TCR_EL1_EPD0_FIELD)\r
-#define TCR_EL1_IRGN0_MASK (0x3 << TCR_EL1_IRGN0_FIELD)\r
-#define TCR_EL1_ORGN0_MASK (0x3 << TCR_EL1_ORGN0_FIELD)\r
-#define TCR_EL1_SH0_MASK (0x3 << TCR_EL1_SH0_FIELD)\r
-#define TCR_EL1_TG0_MASK (0x1 << TCR_EL1_TG0_FIELD)\r
-#define TCR_EL1_T1SZ_MASK (0x1F << TCR_EL1_T1SZ_FIELD)\r
-#define TCR_EL1_A1_MASK (0x1 << TCR_EL1_A1_FIELD)\r
-#define TCR_EL1_EPD1_MASK (0x1 << TCR_EL1_EPD1_FIELD)\r
-#define TCR_EL1_IRGN1_MASK (0x3 << TCR_EL1_IRGN1_FIELD)\r
-#define TCR_EL1_ORGN1_MASK (0x3 << TCR_EL1_ORGN1_FIELD)\r
-#define TCR_EL1_SH1_MASK (0x3 << TCR_EL1_SH1_FIELD)\r
-#define TCR_EL1_TG1_MASK (0x1 << TCR_EL1_TG1_FIELD)\r
-#define TCR_EL1_IPS_MASK (0x7 << TCR_EL1_IPS_FIELD)\r
-#define TCR_EL1_AS_MASK (0x1 << TCR_EL1_AS_FIELD)\r
-#define TCR_EL1_TBI0_MASK (0x1 << TCR_EL1_TBI0_FIELD)\r
-#define TCR_EL1_TBI1_MASK (0x1 << TCR_EL1_TBI1_FIELD)\r
-\r
-\r
-#define VTCR_EL23_T0SZ_FIELD (0)\r
-#define VTCR_EL23_IRGN0_FIELD (8)\r
-#define VTCR_EL23_ORGN0_FIELD (10)\r
-#define VTCR_EL23_SH0_FIELD (12)\r
+#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)\r
+#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)\r
+#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)\r
+#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)\r
+#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)\r
+#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)\r
+#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)\r
+#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)\r
+#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)\r
+#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)\r
+#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)\r
+#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)\r
+#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)\r
+#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)\r
+#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)\r
+#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)\r
+#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)\r
+\r
+\r
+#define TCR_EL23_T0SZ_FIELD (0)\r
+#define TCR_EL23_IRGN0_FIELD (8)\r
+#define TCR_EL23_ORGN0_FIELD (10)\r
+#define TCR_EL23_SH0_FIELD (12)\r
#define TCR_EL23_TG0_FIELD (14)\r
-#define VTCR_EL23_PS_FIELD (16)\r
-#define TCR_EL23_T0SZ_MASK (0x1F << VTCR_EL23_T0SZ_FIELD)\r
-#define TCR_EL23_IRGN0_MASK (0x3 << VTCR_EL23_IRGN0_FIELD)\r
-#define TCR_EL23_ORGN0_MASK (0x3 << VTCR_EL23_ORGN0_FIELD)\r
-#define TCR_EL23_SH0_MASK (0x3 << VTCR_EL23_SH0_FIELD)\r
-#define TCR_EL23_TG0_MASK (0x1 << TCR_EL23_TG0_FIELD)\r
-#define TCR_EL23_PS_MASK (0x7 << VTCR_EL23_PS_FIELD)\r
-\r
-\r
-#define VTCR_EL2_T0SZ_FIELD (0)\r
-#define VTCR_EL2_SL0_FIELD (6)\r
-#define VTCR_EL2_IRGN0_FIELD (8)\r
-#define VTCR_EL2_ORGN0_FIELD (10)\r
-#define VTCR_EL2_SH0_FIELD (12)\r
-#define VTCR_EL2_TG0_FIELD (14)\r
-#define VTCR_EL2_PS_FIELD (16)\r
-#define VTCR_EL2_T0SZ_MASK (0x1F << VTCR_EL2_T0SZ_FIELD)\r
-#define VTCR_EL2_SL0_MASK (0x1F << VTCR_EL2_SL0_FIELD)\r
-#define VTCR_EL2_IRGN0_MASK (0x3 << VTCR_EL2_IRGN0_FIELD)\r
-#define VTCR_EL2_ORGN0_MASK (0x3 << VTCR_EL2_ORGN0_FIELD)\r
-#define VTCR_EL2_SH0_MASK (0x3 << VTCR_EL2_SH0_FIELD)\r
-#define VTCR_EL2_TG0_MASK (0x1 << VTCR_EL2_TG0_FIELD)\r
-#define VTCR_EL2_PS_MASK (0x7 << VTCR_EL2_PS_FIELD)\r
-\r
-\r
-#define TCR_RGN_OUTER_NON_CACHEABLE (0x0 << 10)\r
-#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1 << 10)\r
-#define TCR_RGN_OUTER_WRITE_THROUGH (0x2 << 10)\r
-#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3 << 10)\r
-\r
-#define TCR_RGN_INNER_NON_CACHEABLE (0x0 << 8)\r
-#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1 << 8)\r
-#define TCR_RGN_INNER_WRITE_THROUGH (0x2 << 8)\r
-#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3 << 8)\r
-\r
-#define TCR_SH_NON_SHAREABLE (0x0 << 12)\r
-#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)\r
-#define TCR_SH_INNER_SHAREABLE (0x3 << 12)\r
-\r
-#define TCR_PASZ_32BITS_4GB (0x0)\r
-#define TCR_PASZ_36BITS_64GB (0x1)\r
-#define TCR_PASZ_40BITS_1TB (0x2)\r
-#define TCR_PASZ_42BITS_4TB (0x3)\r
-#define TCR_PASZ_44BITS_16TB (0x4)\r
-#define TCR_PASZ_48BITS_256TB (0x5)\r
+#define TCR_EL23_PS_FIELD (16)\r
+#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)\r
+#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)\r
+#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)\r
+#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)\r
+#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)\r
+#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)\r
+\r
+\r
+#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)\r
+\r
+#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)\r
+#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)\r
+#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)\r
+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)\r
+\r
+#define TCR_SH_NON_SHAREABLE (0x0UL << 12)\r
+#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)\r
+#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)\r
+\r
+#define TCR_PASZ_32BITS_4GB (0x0UL)\r
+#define TCR_PASZ_36BITS_64GB (0x1UL)\r
+#define TCR_PASZ_40BITS_1TB (0x2UL)\r
+#define TCR_PASZ_42BITS_4TB (0x3UL)\r
+#define TCR_PASZ_44BITS_16TB (0x4UL)\r
+#define TCR_PASZ_48BITS_256TB (0x5UL)\r
\r
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit\r
// Virtual address range for 512GB of virtual space sets T*SZ to 25\r
projects / mirror_edk2.git / blobdiff