#define TT_NS BIT5\r
#define TT_AF BIT10\r
\r
+#define TT_SH_NON_SHAREABLE (0x0 << 8)\r
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)\r
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)\r
+#define TT_SH_MASK (0x3 << 8)\r
+\r
#define TT_PXN_MASK BIT53\r
#define TT_UXN_MASK BIT54 // EL1&0\r
#define TT_XN_MASK BIT54 // EL2 / EL3\r
#define TCR_PS_256TB (5 << 16)\r
\r
#define TCR_TG0_4KB (0 << 14)\r
+#define TCR_TG1_4KB (2 << 30)\r
\r
#define TCR_IPS_4GB (0ULL << 32)\r
#define TCR_IPS_64GB (1ULL << 32)\r
#define TCR_IPS_16TB (4ULL << 32)\r
#define TCR_IPS_256TB (5ULL << 32)\r
\r
+#define TCR_EPD1 (1 << 23)\r
\r
#define TTBR_ASID_FIELD (48)\r
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)\r