//\r
// Cortex A9 Watchdog\r
//\r
-#define ARM_A9_WATCHDOG_REGION 0x600\r
+#define ARM_A9_WATCHDOG_REGION 0x600\r
\r
-#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r
-#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r
+#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r
+#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r
\r
-#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r
-#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r
-#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r
-#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r
-#define ARM_A9_WATCHDOG_ENABLE 1\r
+#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r
+#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r
+#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r
+#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r
+#define ARM_A9_WATCHDOG_ENABLE 1\r
\r
//\r
// SCU register offsets & masks\r
//\r
-#define A9_SCU_CONTROL_OFFSET 0x0\r
-#define A9_SCU_CONFIG_OFFSET 0x4\r
-#define A9_SCU_INVALL_OFFSET 0xC\r
-#define A9_SCU_FILT_START_OFFSET 0x40\r
-#define A9_SCU_FILT_END_OFFSET 0x44\r
-#define A9_SCU_SACR_OFFSET 0x50\r
-#define A9_SCU_SSACR_OFFSET 0x54\r
-\r
+#define A9_SCU_CONTROL_OFFSET 0x0\r
+#define A9_SCU_CONFIG_OFFSET 0x4\r
+#define A9_SCU_INVALL_OFFSET 0xC\r
+#define A9_SCU_FILT_START_OFFSET 0x40\r
+#define A9_SCU_FILT_END_OFFSET 0x44\r
+#define A9_SCU_SACR_OFFSET 0x50\r
+#define A9_SCU_SSACR_OFFSET 0x54\r
\r
UINTN\r
EFIAPI\r
);\r
\r
#endif // ARM_CORTEX_A9_H_\r
-\r