ArmPkg/ArmLib: Clean ArmV7Lib

[mirror_edk2.git] / ArmPkg / Include / Chipset / ArmV7.h

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 5fab7eddbe82acf62a3f33d7125329507bd1950c..909686ce361abda8f42cf2a53fb341691b2c0a47 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -1,6 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -24,28 +25,6 @@
 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))\r
 \r
-// Cortex A9 feature bit definitions\r
-#define A9_FEATURE_PARITY  (1<<9)\r
-#define A9_FEATURE_AOW     (1<<8)\r
-#define A9_FEATURE_EXCL    (1<<7)\r
-#define A9_FEATURE_SMP     (1<<6)\r
-#define A9_FEATURE_FOZ     (1<<3)\r
-#define A9_FEATURE_DPREF   (1<<2)\r
-#define A9_FEATURE_HINT    (1<<1)\r
-#define A9_FEATURE_FWD     (1<<0)\r
-\r
-// SCU register offsets & masks\r
-#define SCU_CONTROL_OFFSET       0x0\r
-#define SCU_CONFIG_OFFSET        0x4\r
-#define SCU_INVALL_OFFSET        0xC\r
-#define SCU_FILT_START_OFFSET    0x40\r
-#define SCU_FILT_END_OFFSET      0x44\r
-#define SCU_SACR_OFFSET          0x50\r
-#define SCU_SSACR_OFFSET         0x54\r
-\r
-#define SMP_GIC_CPUIF_BASE       0x100\r
-#define SMP_GIC_DIST_BASE        0x1000\r
-\r
 // CPACR - Coprocessor Access Control Register definitions\r
 #define CPACR_CP_DENIED(cp)     0x00\r
 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
@@ -71,121 +50,24 @@
 #define SCR_FW                  (1 << 4)\r
 #define SCR_AW                  (1 << 5)\r
 \r
-VOID\r
-EFIAPI\r
-ArmEnableSWPInstruction (\r
-  VOID\r
-  );\r
+// MIDR - Main ID Register definitions\r
+#define ARM_CPU_TYPE_MASK       0xFFF\r
+#define ARM_CPU_TYPE_A15        0xC0F\r
+#define ARM_CPU_TYPE_A9         0xC09\r
+#define ARM_CPU_TYPE_A5         0xC05\r
 \r
 VOID\r
 EFIAPI\r
-ArmWriteNsacr (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteScr (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVMBar (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVBar (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmReadVBar (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCPACR (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmEnableVFP (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCallWFI (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidScu (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmGetScuBaseAddress (\r
-  VOID\r
-  );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmIsScuEnable (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteAuxCr (\r
-  IN  UINT32    Bit\r
-  );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmReadAuxCr (\r
+ArmEnableSWPInstruction (\r
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmSetAuxCrBit (\r
-  IN  UINT32    Bits\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmSetupSmpNonSecure (\r
-  IN  UINTN                     CoreId\r
-  );\r
-\r
 UINTN \r
 EFIAPI\r
 ArmReadCbar (\r
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmInvalidateInstructionAndDataTlb (\r
-  VOID\r
-  );\r
-\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadMpidr (\r
-  VOID\r
-  );\r
-\r
 UINTN\r
 EFIAPI\r
 ArmReadTpidrurw (\r
@@ -198,4 +80,10 @@ ArmWriteTpidrurw (
   UINTN Value\r
   );\r
 \r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr1 (\r
+  VOID\r
+  );\r
+  \r
 #endif // __ARM_V7_H__\r