#ifndef __ARM_V7_H__\r
#define __ARM_V7_H__\r
\r
+#include <Chipset/ArmV7Mmu.h>\r
+\r
// Domain Access Control Register\r
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
\r
-#define TRANSLATION_TABLE_SIZE (16 * 1024)\r
-#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)\r
-#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
-\r
-// Translation table descriptor types\r
-#define TT_DESCRIPTOR_TYPE_MASK ((1UL << 18) | (3UL << 0))\r
-#define TT_DESCRIPTOR_TYPE_PAGE_TABLE ((0UL << 18) | (1UL << 0))\r
-#define TT_DESCRIPTOR_TYPE_SECTION ((0UL << 18) | (2UL << 0))\r
-#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
-\r
-// Section descriptor definitions\r
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)\r
-\r
-#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)\r
-\r
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))\r
-\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)\r
-\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
-\r
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_DEVICE (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
+// Cortex A9 feature bit definitions\r
+#define A9_FEATURE_PARITY (1<<9)\r
+#define A9_FEATURE_AOW (1<<8)\r
+#define A9_FEATURE_EXCL (1<<7)\r
+#define A9_FEATURE_SMP (1<<6)\r
+#define A9_FEATURE_FOZ (1<<3)\r
+#define A9_FEATURE_DPREF (1<<2)\r
+#define A9_FEATURE_HINT (1<<1)\r
+#define A9_FEATURE_FWD (1<<0)\r
+\r
+// SCU register offsets & masks\r
+#define SCU_CONTROL_OFFSET 0x0\r
+#define SCU_CONFIG_OFFSET 0x4\r
+#define SCU_INVALL_OFFSET 0xC\r
+#define SCU_FILT_START_OFFSET 0x40\r
+#define SCU_FILT_END_OFFSET 0x44\r
+#define SCU_SACR_OFFSET 0x50\r
+#define SCU_SSACR_OFFSET 0x54\r
+\r
+#define SMP_GIC_CPUIF_BASE 0x100\r
+#define SMP_GIC_DIST_BASE 0x1000\r
+\r
+// CPACR - Coprocessor Access Control Register definitions\r
+#define CPACR_CP_DENIED(cp) 0x00\r
+#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
+#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r
+#define CPACR_ASEDIS (1 << 31)\r
+#define CPACR_D32DIS (1 << 30)\r
+#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r
+\r
+// NSACR - Non-Secure Access Control Register definitions\r
+#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r
+#define NSACR_NSD32DIS (1 << 14)\r
+#define NSACR_NSASEDIS (1 << 15)\r
+#define NSACR_PLE (1 << 16)\r
+#define NSACR_TL (1 << 17)\r
+#define NSACR_NS_SMP (1 << 18)\r
+#define NSACR_RFR (1 << 19)\r
+\r
+// SCR - Secure Configuration Register definitions\r
+#define SCR_NS (1 << 0)\r
+#define SCR_IRQ (1 << 1)\r
+#define SCR_FIQ (1 << 2)\r
+#define SCR_EA (1 << 3)\r
+#define SCR_FW (1 << 4)\r
+#define SCR_AW (1 << 5)\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableSWPInstruction (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteNsacr (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteScr (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteVMBar (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteVBar (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadVBar (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCPACR (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableVFP (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCallWFI (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidScu (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGetScuBaseAddress (\r
+ VOID\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmIsScuEnable (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteAuxCr (\r
+ IN UINT32 Bit\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadAuxCr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetAuxCrBit (\r
+ IN UINT32 Bits\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetupSmpNonSecure (\r
+ IN UINTN CoreId\r
+ );\r
+\r
+UINTN \r
+EFIAPI\r
+ArmReadCbar (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateInstructionAndDataTlb (\r
+ VOID\r
+ );\r
+\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadMpidr (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadTpidrurw (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteTpidrurw (\r
+ UINTN Value\r
+ );\r
\r
#endif // __ARM_V7_H__\r
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