/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#define __ARM_V7_H__\r
\r
#include <Chipset/ArmV7Mmu.h>\r
-#include <Chipset/ArmArchTimer.h>\r
\r
// ARM Interrupt ID in Exception Table\r
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r
#define SCR_AW (1 << 5)\r
\r
// MIDR - Main ID Register definitions\r
+#define ARM_CPU_TYPE_SHIFT 4\r
#define ARM_CPU_TYPE_MASK 0xFFF\r
#define ARM_CPU_TYPE_AEMv8 0xD0F\r
#define ARM_CPU_TYPE_A53 0xD03\r
#define ARM_CPU_TYPE_A57 0xD07\r
#define ARM_CPU_TYPE_A15 0xC0F\r
+#define ARM_CPU_TYPE_A12 0xC0D\r
#define ARM_CPU_TYPE_A9 0xC09\r
+#define ARM_CPU_TYPE_A7 0xC07\r
#define ARM_CPU_TYPE_A5 0xC05\r
\r
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
VOID\r
);\r
\r
-UINTN \r
+UINTN\r
EFIAPI\r
ArmReadCbar (\r
VOID\r