/** @file\r
*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
#ifndef __ARMGIC_H\r
#define __ARMGIC_H\r
\r
-//\r
-// GIC definitions\r
-//\r
+#include <Library/ArmGicArchLib.h>\r
\r
//\r
// GIC Distributor\r
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
\r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
\r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
+// Each reg base below repeats for Number of interrupts / 4\r
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
\r
-// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
+// Each reg base below repeats for Number of interrupts\r
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
\r
// just one of these\r
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
\r
+// GICv3 specific registers\r
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
+\r
+// GICD_CTLR bits\r
+#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
+#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
+\r
+//\r
+// GIC Redistributor\r
+//\r
+\r
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
+\r
+// GIC Redistributor Control frame\r
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
+\r
+// GIC SGI & PPI Redistributor frame\r
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
+\r
//\r
// GIC Cpu interface\r
//\r
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
\r
+// Bit Mask for\r
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
+\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
IN INTN SgiId\r
);\r
\r
+/*\r
+ * Acknowledge and return the value of the Interrupt Acknowledge Register\r
+ *\r
+ * InterruptId is returned separately from the register value because in\r
+ * the GICv2 the register value contains the CpuId and InterruptId while\r
+ * in the GICv3 the register value is only the InterruptId.\r
+ *\r
+ * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
+ * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
+ *\r
+ * @retval value returned by the Interrupt Acknowledge Register\r
+ *\r
+ */\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *InterruptId\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
IN UINTN Source\r
);\r
\r
EFIAPI\r
ArmGicDisableInterrupt (\r
IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
IN UINTN Source\r
);\r
\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
+//\r
+// GIC revision 2 specific declarations\r
+//\r
+\r
+// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2SetupNonSecure (\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2DisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV2AcknowledgeInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EndOfInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase,\r
IN UINTN Source\r
);\r
\r
+//\r
+// GIC revision 3 specific declarations\r
+//\r
+\r
+#define ICC_SRE_EL2_SRE (1 << 0)\r
+\r
+#define ARM_GICD_IROUTER_IRM BIT31\r
+\r
+UINT32\r
+EFIAPI\r
+ArmGicV3GetControlSystemRegisterEnable (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3SetControlSystemRegisterEnable (\r
+ IN UINT32 ControlSystemRegisterEnable\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3EnableInterruptInterface (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3DisableInterruptInterface (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV3AcknowledgeInterrupt (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3EndOfInterrupt (\r
+ IN UINTN Source\r
+ );\r
+\r
+VOID\r
+ArmGicV3SetBinaryPointer (\r
+ IN UINTN BinaryPoint\r
+ );\r
+\r
+VOID\r
+ArmGicV3SetPriorityMask (\r
+ IN UINTN Priority\r
+ );\r
+\r
#endif\r
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