/** @file\r
*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
//\r
// GIC definitions\r
//\r
+typedef enum {\r
+ ARM_GIC_ARCH_REVISION_2\r
+} ARM_GIC_ARCH_REVISION;\r
\r
//\r
// GIC Distributor\r
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
-#define ARM_GIC_ICCIDR 0xFC // Identification Register\r
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
\r
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
\r
// Bit Mask for GICC_IIDR\r
-#define ARM_GIC_ICCIDR_GET_PRODUCT_ID(IccIdr) (((IccIdr) >> 20) & 0xFFF)\r
-#define ARM_GIC_ICCIDR_GET_ARCH_VERSION(IccIdr) (((IccIdr) >> 16) & 0xF)\r
-#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr) (((IccIdr) >> 12) & 0xF)\r
-#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr) ((IccIdr) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicGetInterfaceIdentification (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
\r
//\r
// GIC Secure interfaces\r
IN INTN GicDistributorBase\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmGicDisableDistributor (\r
+ IN INTN GicDistributorBase\r
+ );\r
+\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
IN INTN SgiId\r
);\r
\r
-RETURN_STATUS\r
+/*\r
+ * Acknowledge and return the value of the Interrupt Acknowledge Register\r
+ *\r
+ * InterruptId is returned separately from the register value because in\r
+ * the GICv2 the register value contains the CpuId and InterruptId while\r
+ * in the GICv3 the register value is only the InterruptId.\r
+ *\r
+ * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
+ * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
+ *\r
+ * @retval value returned by the Interrupt Acknowledge Register\r
+ *\r
+ */\r
+UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicDistributorBase,\r
IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *CoreId,\r
OUT UINTN *InterruptId\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmGicEndOfInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
+ );\r
+\r
UINTN\r
EFIAPI\r
ArmGicSetPriorityMask (\r
IN INTN PriorityMask\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterrupt (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterrupt (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmGicIsInterruptEnabled (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
#endif\r