//\r
// GIC definitions\r
//\r
+typedef enum {\r
+ ARM_GIC_ARCH_REVISION_2\r
+} ARM_GIC_ARCH_REVISION;\r
\r
//\r
// GIC Distributor\r
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+ VOID\r
+ );\r
+\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
IN INTN SgiId\r
);\r
\r
+/*\r
+ * Acknowledge and return the value of the Interrupt Acknowledge Register\r
+ *\r
+ * InterruptId is returned separately from the register value because in\r
+ * the GICv2 the register value contains the CpuId and InterruptId while\r
+ * in the GICv3 the register value is only the InterruptId.\r
+ *\r
+ * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
+ * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
+ *\r
+ * @retval value returned by the Interrupt Acknowledge Register\r
+ *\r
+ */\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *InterruptId\r
);\r
\r
VOID\r