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[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index e762489e2f517925ac59deee214efbe84c30e52c..23beb242749cfe41d5fb03098a684f324130ab7a 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,8 +1,9 @@
 /** @file
 
-  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
 
-  All rights reserved. This program and the accompanying materials
+  This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
   http://opensource.org/licenses/bsd-license.php
@@ -15,6 +16,14 @@
 #ifndef __ARM_LIB__
 #define __ARM_LIB__
 
+#include <Uefi/UefiBaseType.h>
+
+#ifdef ARM_CPU_ARMv6
+#include <Chipset/ARM1176JZ-S.h>
+#else
+#include <Chipset/ArmV7.h>
+#endif
+
 typedef enum {
   ARM_CACHE_TYPE_WRITE_BACK,
   ARM_CACHE_TYPE_UNKNOWN
@@ -39,34 +48,80 @@ typedef struct {
   UINTN                   InstructionCacheLineLength;
 } ARM_CACHE_INFO;
 
+/**
+ * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
+ *
+ * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
+ * be used in Secure World to distinguished Secure to Non-Secure memory.
+ */
 typedef enum {
-  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
+  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
+  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
+  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
-  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
+  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
+  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
 } ARM_MEMORY_REGION_ATTRIBUTES;
 
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
+
 typedef struct {
-  UINT32                        PhysicalBase;
-  UINT32                        VirtualBase;
-  UINT32                        Length;
+  EFI_PHYSICAL_ADDRESS          PhysicalBase;
+  EFI_VIRTUAL_ADDRESS           VirtualBase;
+  UINTN                         Length;
   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
 } ARM_MEMORY_REGION_DESCRIPTOR;
 
 typedef VOID (*CACHE_OPERATION)(VOID);
 typedef VOID (*LINE_OPERATION)(UINTN);
 
+//
+// ARM Processor Mode
+//
 typedef enum {
   ARM_PROCESSOR_MODE_USER       = 0x10,
   ARM_PROCESSOR_MODE_FIQ        = 0x11,
   ARM_PROCESSOR_MODE_IRQ        = 0x12,
   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
   ARM_PROCESSOR_MODE_ABORT      = 0x17,
+  ARM_PROCESSOR_MODE_HYP        = 0x1A,
   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
   ARM_PROCESSOR_MODE_MASK       = 0x1F
 } ARM_PROCESSOR_MODE;
 
+//
+// ARM Cpu IDs
+//
+#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
+#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
+#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
+#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
+#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
+#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
+
+#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
+
+//
+// ARM MP Core IDs
+//
+#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
+#define ARM_CORE_MASK         0xFF
+#define ARM_CLUSTER_MASK      (0xFF << 8)
+#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
+// Get the position of the core for the Stack Offset (4 Core per Cluster)
+//   Position = (ClusterId * 4) + CoreId
+#define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
+#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+
 ARM_CACHE_TYPE
 EFIAPI
 ArmCacheType (
@@ -145,6 +200,12 @@ Cp15CacheInfo (
   VOID
   );
 
+BOOLEAN
+EFIAPI
+ArmIsMpCore (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmInvalidateDataCache (
@@ -164,6 +225,12 @@ ArmCleanDataCache (
   VOID
   );
 
+VOID
+EFIAPI
+ArmCleanDataCacheToPoU (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmInvalidateInstructionCache (
@@ -224,6 +291,18 @@ ArmDisableMmu (
   VOID
   );
 
+VOID
+EFIAPI
+ArmDisableCachesAndMmu (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmInvalidateInstructionAndDataTlb (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmEnableInterrupts (
@@ -241,6 +320,7 @@ EFIAPI
 ArmGetInterruptState (
   VOID
   );
+
 VOID
 EFIAPI
 ArmEnableFiq (
@@ -268,7 +348,8 @@ ArmInvalidateTlb (
 VOID
 EFIAPI
 ArmUpdateTranslationTableEntry (
-  IN  UINTN    Mva
+  IN  VOID     *TranslationTableEntry,
+  IN  VOID     *Mva
   );
   
 VOID
@@ -279,13 +360,13 @@ ArmSetDomainAccessControl (
 
 VOID
 EFIAPI
-ArmSetTranslationTableBaseAddress (
+ArmSetTTBR0 (
   IN  VOID  *TranslationTableBase
   );
 
 VOID *
 EFIAPI
-ArmGetTranslationTableBaseAddress (
+ArmGetTTBR0BaseAddress (
   VOID
   );
 
@@ -326,7 +407,19 @@ EFIAPI
 ArmDisableBranchPrediction (
   VOID
   );
-  
+
+VOID
+EFIAPI
+ArmSetLowVectors (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmSetHighVectors (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmDataMemoryBarrier (
@@ -344,5 +437,125 @@ EFIAPI
 ArmInstructionSynchronizationBarrier (
   VOID
   );
-  
+
+VOID
+EFIAPI
+ArmWriteVBar (
+  IN  UINT32   VectorBase
+  );
+
+UINT32
+EFIAPI
+ArmReadVBar (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteAuxCr (
+  IN  UINT32    Bit
+  );
+
+UINT32
+EFIAPI
+ArmReadAuxCr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmSetAuxCrBit (
+  IN  UINT32    Bits
+  );
+
+VOID
+EFIAPI
+ArmUnsetAuxCrBit (
+  IN  UINT32    Bits
+  );
+
+VOID
+EFIAPI
+ArmCallSEV (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmCallWFE (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmCallWFI (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmReadMpidr (
+  VOID
+  );
+
+UINT32
+EFIAPI
+ArmReadCpacr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteCpacr (
+  IN  UINT32   Access
+  );
+
+VOID
+EFIAPI
+ArmEnableVFP (
+  VOID
+  );
+
+UINT32
+EFIAPI
+ArmReadNsacr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteNsacr (
+  IN  UINT32   SetWayFormat
+  );
+
+UINT32
+EFIAPI
+ArmReadScr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteScr (
+  IN  UINT32   SetWayFormat
+  );
+
+UINT32
+EFIAPI
+ArmReadMVBar (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteMVBar (
+  IN  UINT32   VectorMonitorBase
+  );
+
+UINT32
+EFIAPI
+ArmReadSctlr (
+  VOID
+  );
+
 #endif // __ARM_LIB__