typedef VOID (*CACHE_OPERATION)(VOID);
typedef VOID (*LINE_OPERATION)(UINTN);
+//
+// ARM Processor Mode
+//
typedef enum {
ARM_PROCESSOR_MODE_USER = 0x10,
ARM_PROCESSOR_MODE_FIQ = 0x11,
ARM_PROCESSOR_MODE_MASK = 0x1F
} ARM_PROCESSOR_MODE;
+//
+// ARM Cpu IDs
+//
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
+
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
+
+//
+// ARM MP Core IDs
+//
#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
-#define GET_CORE_ID(MpId) ((MpId) & 0xFF)
-#define GET_CLUSTER_ID(MpId) (((MpId) >> 8) & 0xFF)
+#define ARM_CORE_MASK 0xFF
+#define ARM_CLUSTER_MASK (0xFF << 8)
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
// Get the position of the core for the Stack Offset (4 Core per Cluster)
// Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0xFF) + ((MpId) & 0xFF))
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0xFF)
+#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
ARM_CACHE_TYPE
EFIAPI