ArmPkg/AArch64Mmu: don't let table entries inherit XN permission bits

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index c8b3d4a121b118bf3b15f7f2890dd3c5aeafc989..cf9b7222b47b2d0bbc85414dec01c04ee33f4ca8 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -50,7 +50,10 @@ ArmMemoryAttributeToPageAttribute (
     ASSERT(0);\r
   case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
-    return TT_ATTR_INDX_DEVICE_MEMORY;\r
+    if (ArmReadCurrentEL () == AARCH64_EL2)\r
+      return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
+    else\r
+      return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
   }\r
 }\r
 \r
@@ -164,6 +167,20 @@ GetRootTranslationTableInfo (
   }\r
 }\r
 \r
+STATIC\r
+VOID\r
+ReplaceLiveEntry (\r
+  IN  UINT64  *Entry,\r
+  IN  UINT64  Value\r
+  )\r
+{\r
+  if (!ArmMmuEnabled ()) {\r
+    *Entry = Value;\r
+  } else {\r
+    ArmReplaceLiveTranslationEntry (Entry, Value);\r
+  }\r
+}\r
+\r
 STATIC\r
 VOID\r
 LookupAddresstoRootTable (\r
@@ -289,13 +306,6 @@ GetBlockEntryListFromAddress (
 \r
         // Convert the block entry attributes into Table descriptor attributes\r
         TableAttributes = TT_TABLE_AP_NO_PERMISSION;\r
-        if (Attributes & TT_PXN_MASK) {\r
-          TableAttributes = TT_TABLE_PXN;\r
-        }\r
-        // XN maps to UXN in the EL1&0 translation regime\r
-        if (Attributes & TT_XN_MASK) {\r
-          TableAttributes = TT_TABLE_XN;\r
-        }\r
         if (Attributes & TT_NS) {\r
           TableAttributes = TT_TABLE_NS;\r
         }\r
@@ -327,7 +337,8 @@ GetBlockEntryListFromAddress (
         }\r
 \r
         // Fill the BlockEntry with the new TranslationTable\r
-        *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;\r
+        ReplaceLiveEntry (BlockEntry,\r
+          ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY);\r
       }\r
     } else {\r
       if (IndexLevel != PageLevel) {\r
@@ -555,7 +566,7 @@ ArmClearMemoryRegionReadOnly (
   return SetMemoryRegionAttribute (\r
            BaseAddress,\r
            Length,\r
-           TT_AP_NO_RO,\r
+           TT_AP_RW_RW,\r
            ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));\r
 }\r
 \r
@@ -625,7 +636,8 @@ ArmConfigureMmu (
       return RETURN_UNSUPPORTED;\r
     }\r
   } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
-    TCR = T0SZ | TCR_TG0_4KB;\r
+    // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.\r
+    TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;\r
 \r
     // Set the Physical Address Size using MaxAddress\r
     if (MaxAddress < SIZE_4GB) {\r