UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmLibPrivate.h

diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
index fdd5a26ba03ff76ba691e91e1a5d96c8ec5c53d7..7fb27068cecf89cfaa59b9e02eb591df16f5551e 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
+++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
@@ -1,33 +1,29 @@
 /** @file\r
+  ArmLibPrivate.h\r
 \r
+  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 \r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
-#ifndef __ARM_LIB_PRIVATE_H__\r
-#define __ARM_LIB_PRIVATE_H__\r
+#ifndef ARM_LIB_PRIVATE_H_\r
+#define ARM_LIB_PRIVATE_H_\r
 \r
-#define CACHE_SIZE_4_KB             (3UL)\r
-#define CACHE_SIZE_8_KB             (4UL)\r
-#define CACHE_SIZE_16_KB            (5UL)\r
-#define CACHE_SIZE_32_KB            (6UL)\r
-#define CACHE_SIZE_64_KB            (7UL)\r
-#define CACHE_SIZE_128_KB           (8UL)\r
+#define CACHE_SIZE_4_KB    (3UL)\r
+#define CACHE_SIZE_8_KB    (4UL)\r
+#define CACHE_SIZE_16_KB   (5UL)\r
+#define CACHE_SIZE_32_KB   (6UL)\r
+#define CACHE_SIZE_64_KB   (7UL)\r
+#define CACHE_SIZE_128_KB  (8UL)\r
 \r
 #define CACHE_ASSOCIATIVITY_DIRECT  (0UL)\r
 #define CACHE_ASSOCIATIVITY_4_WAY   (2UL)\r
 #define CACHE_ASSOCIATIVITY_8_WAY   (3UL)\r
 \r
-#define CACHE_PRESENT               (0UL)\r
-#define CACHE_NOT_PRESENT           (1UL)\r
+#define CACHE_PRESENT      (0UL)\r
+#define CACHE_NOT_PRESENT  (1UL)\r
 \r
 #define CACHE_LINE_LENGTH_32_BYTES  (2UL)\r
 \r
@@ -36,25 +32,25 @@
 #define SIZE_FIELD_TO_CACHE_PRESENCE(x)       (((x) >> 2) & 0x01)\r
 #define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x)    (((x) >> 0) & 0x03)\r
 \r
-#define DATA_CACHE_SIZE_FIELD(x)              (((x) >> 12) & 0x0FFF)\r
-#define INSTRUCTION_CACHE_SIZE_FIELD(x)       (((x) >>  0) & 0x0FFF)\r
+#define DATA_CACHE_SIZE_FIELD(x)         (((x) >> 12) & 0x0FFF)\r
+#define INSTRUCTION_CACHE_SIZE_FIELD(x)  (((x) >>  0) & 0x0FFF)\r
 \r
-#define DATA_CACHE_SIZE(x)                    (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_ASSOCIATIVITY(x)           (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_PRESENT(x)                 (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_LINE_LENGTH(x)             (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_SIZE(x)           (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_ASSOCIATIVITY(x)  (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_PRESENT(x)        (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_LINE_LENGTH(x)    (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
 \r
-#define INSTRUCTION_CACHE_SIZE(x)             (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x)    (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_PRESENT(x)          (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_LINE_LENGTH(x)      (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_SIZE(x)           (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x)  (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_PRESENT(x)        (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_LINE_LENGTH(x)    (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
 \r
-#define CACHE_TYPE(x)                         (((x) >> 25) & 0x0F)\r
-#define CACHE_TYPE_WRITE_BACK                 (0x0EUL)\r
+#define CACHE_TYPE(x)  (((x) >> 25) & 0x0F)\r
+#define CACHE_TYPE_WRITE_BACK  (0x0EUL)\r
 \r
-#define CACHE_ARCHITECTURE(x)                 (((x) >> 24) & 0x01)\r
-#define CACHE_ARCHITECTURE_UNIFIED            (0UL)\r
-#define CACHE_ARCHITECTURE_SEPARATE           (1UL)\r
+#define CACHE_ARCHITECTURE(x)  (((x) >> 24) & 0x01)\r
+#define CACHE_ARCHITECTURE_UNIFIED   (0UL)\r
+#define CACHE_ARCHITECTURE_SEPARATE  (1UL)\r
 \r
 VOID\r
 CPSRMaskInsert (\r
@@ -67,14 +63,4 @@ CPSRRead (
   VOID\r
   );\r
 \r
-UINT32\r
-ReadCCSIDR (\r
-  IN UINT32 CSSELR\r
-  );\r
-\r
-UINT32\r
-ReadCLIDR (\r
-  VOID\r
-  );\r
-\r
-#endif // __ARM_LIB_PRIVATE_H__\r
+#endif // ARM_LIB_PRIVATE_H_\r