ArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includes

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLib.c

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLib.c b/ArmPkg/Library/ArmLib/Common/ArmLib.c
index 2a2c4e86fd21061fb740400a067f9aa2a44db21f..7e227936fa6fe53dc3f34c79eb77a66e51baedd9 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLib.c
+++ b/ArmPkg/Library/ArmLib/Common/ArmLib.c
@@ -1,7 +1,8 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  \r
+  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -22,39 +23,85 @@
 \r
 VOID\r
 EFIAPI\r
-ArmCacheInformation (\r
-  OUT ARM_CACHE_INFO  *CacheInfo\r
+ArmSetAuxCrBit (\r
+  IN  UINT32    Bits\r
   )\r
 {\r
-  if (CacheInfo != NULL) {\r
-    CacheInfo->Type                           = ArmCacheType();\r
-    CacheInfo->Architecture                   = ArmCacheArchitecture();\r
-    CacheInfo->DataCachePresent               = ArmDataCachePresent();\r
-    CacheInfo->DataCacheSize                  = ArmDataCacheSize();\r
-    CacheInfo->DataCacheAssociativity         = ArmDataCacheAssociativity();\r
-    CacheInfo->DataCacheLineLength            = ArmDataCacheLineLength();\r
-    CacheInfo->InstructionCachePresent        = ArmInstructionCachePresent();\r
-    CacheInfo->InstructionCacheSize           = ArmInstructionCacheSize();\r
-    CacheInfo->InstructionCacheAssociativity  = ArmInstructionCacheAssociativity();\r
-    CacheInfo->InstructionCacheLineLength     = ArmInstructionCacheLineLength();\r
-  }\r
+  UINT32 val = ArmReadAuxCr();\r
+  val |= Bits;\r
+  ArmWriteAuxCr(val);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetAuxCrBit (\r
+  IN  UINT32    Bits\r
+  )\r
+{\r
+  UINT32 val = ArmReadAuxCr();\r
+  val &= ~Bits;\r
+  ArmWriteAuxCr(val);\r
+}\r
+\r
+//\r
+// Helper functions for accessing CPUACTLR\r
+//\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+  IN  UINTN    Bits\r
+  )\r
+{\r
+  UINTN Value;\r
+  Value =  ArmReadCpuActlr ();\r
+  Value |= Bits;\r
+  ArmWriteCpuActlr (Value);\r
 }\r
 \r
 VOID\r
 EFIAPI\r
-ArmSwitchProcessorMode (\r
-  IN ARM_PROCESSOR_MODE Mode\r
+ArmUnsetCpuActlrBit (\r
+  IN  UINTN    Bits\r
   )\r
 {\r
-  CPSRMaskInsert(ARM_PROCESSOR_MODE_MASK, Mode);\r
+  UINTN Value;\r
+  Value = ArmReadCpuActlr ();\r
+  Value &= ~Bits;\r
+  ArmWriteCpuActlr (Value);\r
 }\r
 \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  return 4 << ((ArmCacheInfo () >> 16) & 0xf); // CTR_EL0.DminLine\r
+}\r
 \r
-ARM_PROCESSOR_MODE\r
+UINTN\r
 EFIAPI\r
-ArmProcessorMode (\r
+ArmInstructionCacheLineLength (\r
   VOID\r
   )\r
 {\r
-  return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);\r
+  return 4 << (ArmCacheInfo () & 0xf); // CTR_EL0.IminLine\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmCacheWritebackGranule (\r
+  VOID\r
+  )\r
+{\r
+  UINTN   CWG;\r
+\r
+  CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG\r
+\r
+  if (CWG == 0) {\r
+    return SIZE_2KB;\r
+  }\r
+\r
+  return 4 << CWG;\r
 }\r