ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / AArch64 / ArmMmuLibCore.c

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 4d75788ed2b2356180058d7e3b0a8d0d2e7c5503..ae59e9a7d04e34ba2e328b8afb246e668aea5493 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -357,6 +357,7 @@ UpdateRegionMapping (
   IN  UINT64   RegionLength,\r
   IN  UINT64   AttributeSetMask,\r
   IN  UINT64   AttributeClearMask,\r
+  IN  UINT64   *RootTable,\r
   IN  BOOLEAN  TableIsLive\r
   )\r
 {\r
@@ -373,7 +374,7 @@ UpdateRegionMapping (
            RegionStart + RegionLength,\r
            AttributeSetMask,\r
            AttributeClearMask,\r
-           ArmGetTTBR0BaseAddress (),\r
+           RootTable,\r
            GetRootTableLevel (T0SZ),\r
            TableIsLive\r
            );\r
@@ -391,6 +392,7 @@ FillTranslationTable (
            MemoryRegion->Length,\r
            ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,\r
            0,\r
+           RootTable,\r
            FALSE\r
            );\r
 }\r
@@ -466,6 +468,7 @@ ArmSetMemoryAttributes (
            Length,\r
            PageAttributes,\r
            PageAttributeMask,\r
+           ArmGetTTBR0BaseAddress (),\r
            TRUE\r
            );\r
 }\r
@@ -484,6 +487,7 @@ SetMemoryRegionAttribute (
            Length,\r
            Attributes,\r
            BlockEntryMask,\r
+           ArmGetTTBR0BaseAddress (),\r
            TRUE\r
            );\r
 }\r
@@ -675,14 +679,6 @@ ArmConfigureMmu (
     return EFI_OUT_OF_RESOURCES;\r
   }\r
 \r
-  //\r
-  // We set TTBR0 just after allocating the table to retrieve its location from\r
-  // the subsequent functions without needing to pass this value across the\r
-  // functions. The MMU is only enabled after the translation tables are\r
-  // populated.\r
-  //\r
-  ArmSetTTBR0 (TranslationTable);\r
-\r
   if (TranslationTableBase != NULL) {\r
     *TranslationTableBase = TranslationTable;\r
   }\r
@@ -691,14 +687,17 @@ ArmConfigureMmu (
     *TranslationTableSize = RootTableEntryCount * sizeof (UINT64);\r
   }\r
 \r
-  //\r
-  // Make sure we are not inadvertently hitting in the caches\r
-  // when populating the page tables.\r
-  //\r
-  InvalidateDataCacheRange (\r
-    TranslationTable,\r
-    RootTableEntryCount * sizeof (UINT64)\r
-    );\r
+  if (!ArmMmuEnabled ()) {\r
+    //\r
+    // Make sure we are not inadvertently hitting in the caches\r
+    // when populating the page tables.\r
+    //\r
+    InvalidateDataCacheRange (\r
+      TranslationTable,\r
+      RootTableEntryCount * sizeof (UINT64)\r
+      );\r
+  }\r
+\r
   ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));\r
 \r
   while (MemoryTable->Length != 0) {\r
@@ -723,12 +722,17 @@ ArmConfigureMmu (
     MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)\r
     );\r
 \r
-  ArmDisableAlignmentCheck ();\r
-  ArmEnableStackAlignmentCheck ();\r
-  ArmEnableInstructionCache ();\r
-  ArmEnableDataCache ();\r
+  ArmSetTTBR0 (TranslationTable);\r
+\r
+  if (!ArmMmuEnabled ()) {\r
+    ArmDisableAlignmentCheck ();\r
+    ArmEnableStackAlignmentCheck ();\r
+    ArmEnableInstructionCache ();\r
+    ArmEnableDataCache ();\r
+\r
+    ArmEnableMmu ();\r
+  }\r
 \r
-  ArmEnableMmu ();\r
   return EFI_SUCCESS;\r
 \r
 FreeTranslationTable:\r