ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / AArch64 / ArmMmuLibCore.c

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index c78297084207366b32c135563000c36884f5c04b..6aa970bc0514e6a73f4aee08a4885980f6a90d7d 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -3,6 +3,7 @@
 *\r
 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *  Copyright (c) 2016, Linaro Limited. All rights reserved.\r
+*  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -89,7 +90,7 @@ PageAttributeToGcdAttribute (
   // Determine protection attributes\r
   if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {\r
     // Read only cases map to write-protect\r
-    GcdAttributes |= EFI_MEMORY_WP;\r
+    GcdAttributes |= EFI_MEMORY_RO;\r
   }\r
 \r
   // Process eXecute Never attribute\r
@@ -553,12 +554,10 @@ ArmConfigureMmu (
   )\r
 {\r
   VOID*                         TranslationTable;\r
-  VOID*                         TranslationTableBuffer;\r
   UINT32                        TranslationTableAttribute;\r
   UINT64                        MaxAddress;\r
   UINTN                         T0SZ;\r
   UINTN                         RootTableEntryCount;\r
-  UINTN                         RootTableEntrySize;\r
   UINT64                        TCR;\r
   RETURN_STATUS                 Status;\r
 \r
@@ -643,19 +642,8 @@ ArmConfigureMmu (
   // Set TCR\r
   ArmSetTCR (TCR);\r
 \r
-  // Allocate pages for translation table. Pool allocations are 8 byte aligned,\r
-  // but we may require a higher alignment based on the size of the root table.\r
-  RootTableEntrySize = RootTableEntryCount * sizeof(UINT64);\r
-  if (RootTableEntrySize < EFI_PAGE_SIZE / 2) {\r
-    TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8);\r
-    //\r
-    // Naturally align the root table. Preserves possible NULL value\r
-    //\r
-    TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1;\r
-  } else {\r
-    TranslationTable = AllocatePages (1);\r
-    TranslationTableBuffer = NULL;\r
-  }\r
+  // Allocate pages for translation table\r
+  TranslationTable = AllocatePages (1);\r
   if (TranslationTable == NULL) {\r
     return RETURN_OUT_OF_RESOURCES;\r
   }\r
@@ -669,10 +657,10 @@ ArmConfigureMmu (
   }\r
 \r
   if (TranslationTableSize != NULL) {\r
-    *TranslationTableSize = RootTableEntrySize;\r
+    *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);\r
   }\r
 \r
-  ZeroMem (TranslationTable, RootTableEntrySize);\r
+  ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));\r
 \r
   // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs\r
   ArmDisableMmu ();\r
@@ -689,7 +677,7 @@ ArmConfigureMmu (
     DEBUG_CODE_BEGIN ();\r
       // Find the memory attribute for the Translation Table\r
       if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&\r
-          (UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase +\r
+          (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +\r
                                                           MemoryTable->Length) {\r
         TranslationTableAttribute = MemoryTable->Attributes;\r
       }\r
@@ -718,11 +706,7 @@ ArmConfigureMmu (
   return RETURN_SUCCESS;\r
 \r
 FREE_TRANSLATION_TABLE:\r
-  if (TranslationTableBuffer != NULL) {\r
-    FreePool (TranslationTableBuffer);\r
-  } else {\r
-    FreePages (TranslationTable, 1);\r
-  }\r
+  FreePages (TranslationTable, 1);\r
   return Status;\r
 }\r
 \r