/** @file\r
* File managing the MMU for ARMv7 architecture\r
*\r
-* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r
*\r
* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
// EntryValue: values at bit positions specified by EntryMask\r
EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;\r
- if (Attributes & EFI_MEMORY_XP) {\r
+ if ((Attributes & EFI_MEMORY_XP) != 0) {\r
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;\r
} else {\r
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
// is irrelevant. If no memory attribute is specified, we preserve whatever\r
// memory type is set in the page tables, and update the permission attributes\r
// only.\r
- if (Attributes & EFI_MEMORY_UC) {\r
+ if ((Attributes & EFI_MEMORY_UC) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// map to strongly ordered\r
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
- } else if (Attributes & EFI_MEMORY_WC) {\r
+ } else if ((Attributes & EFI_MEMORY_WC) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// map to normal non-cachable\r
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
- } else if (Attributes & EFI_MEMORY_WT) {\r
+ } else if ((Attributes & EFI_MEMORY_WT) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// write through with no-allocate\r
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
- } else if (Attributes & EFI_MEMORY_WB) {\r
+ } else if ((Attributes & EFI_MEMORY_WB) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
// write back (with allocate)\r
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
- } else if (Attributes & CACHE_ATTRIBUTE_MASK) {\r
+ } else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) {\r
// catch unsupported memory type attributes\r
ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
- if (Attributes & EFI_MEMORY_RO) {\r
+ if ((Attributes & EFI_MEMORY_RO) != 0) {\r
EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;\r
} else {\r
EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;\r
// is irrelevant. If no memory attribute is specified, we preserve whatever\r
// memory type is set in the page tables, and update the permission attributes\r
// only.\r
- if (Attributes & EFI_MEMORY_UC) {\r
+ if ((Attributes & EFI_MEMORY_UC) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// map to strongly ordered\r
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
- } else if (Attributes & EFI_MEMORY_WC) {\r
+ } else if ((Attributes & EFI_MEMORY_WC) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// map to normal non-cachable\r
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
- } else if (Attributes & EFI_MEMORY_WT) {\r
+ } else if ((Attributes & EFI_MEMORY_WT) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// write through with no-allocate\r
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
- } else if (Attributes & EFI_MEMORY_WB) {\r
+ } else if ((Attributes & EFI_MEMORY_WB) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
// write back (with allocate)\r
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
- } else if (Attributes & CACHE_ATTRIBUTE_MASK) {\r
+ } else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) {\r
// catch unsupported memory type attributes\r
ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
- if (Attributes & EFI_MEMORY_RO) {\r
+ if ((Attributes & EFI_MEMORY_RO) != 0) {\r
EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO;\r
} else {\r
EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW;\r
}\r
\r
- if (Attributes & EFI_MEMORY_XP) {\r
+ if ((Attributes & EFI_MEMORY_XP) != 0) {\r
EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;\r
}\r
\r