#\r
gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
\r
+ ## Include/Guid/ArmGlobalVariableHob.h\r
+ gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
+\r
+[Ppis]\r
+ ## Include/Ppi/ArmGlobalVariable.h\r
+ gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
+\r
[PcdsFeatureFlag.common]\r
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
\r
[PcdsFixedAtBuild.common]\r
- # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.\r
- # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003\r
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
# Stack for CPU Cores in Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
\r
+ # Size to reserve in the primary core stack for SEC Global Variables\r
+ gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
+\r
#\r
# ARM Primecells\r
#\r