#/** @file\r
#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
\r
gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
- \r
+\r
+ # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
+ # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
+ gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
+\r
[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
# Stack for CPU Cores in Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
- # Stack for CPU Cores in Secure Monitor Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
-\r
# Stack for CPU Cores in Non Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
# Size to reserve in the primary core stack for SEC Global Variables\r
gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
\r
+ # Boot Monitor FileSystem\r
+ gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
+\r
#\r
# ARM Primecells\r
#\r
gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
# PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: \r
# - 0 = an EFI application\r
# - 1 = a Linux kernel with ATAG support\r
\r
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
- \r
+\r
+[PcdsFixedAtBuild.ARM]\r
+ # Stack for CPU Cores in Secure Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
+ # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
+ # and PcdCPUCoreSecSecondaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
+\r