#/** @file\r
#\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
\r
- ## Include/Guid/ArmGlobalVariableHob.h\r
- gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
-\r
gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
\r
-[Ppis]\r
- ## Include/Ppi/ArmGlobalVariable.h\r
- gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
-\r
[PcdsFeatureFlag.common]\r
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
# we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
\r
+ # Enable Legacy Linux support in the BDS\r
+ gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E\r
+\r
[PcdsFixedAtBuild.common]\r
gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
# Stack for CPU Cores in Non Secure Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
\r
# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
\r
- # Size to reserve in the primary core stack for PEI Global Variables\r
- # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
- gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r
- # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
- # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.\r
- gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
- gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
-\r
- # Size to reserve in the primary core stack for SEC Global Variables\r
- gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
-\r
# Boot Monitor FileSystem\r
gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
\r
gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r
gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
- # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:\r
- # - 0 = an EFI application\r
- # - 1 = a Linux kernel with ATAG support\r
- # - 2 = a Linux kernel with FDT support\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010\r
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011\r
-\r
- ## Timeout value for displaying progressing bar in before boot OS.\r
- # According to UEFI 2.0 spec, the default TimeOut should be 0xffff.\r
- gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A\r
\r
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
+\r
[PcdsFixedAtBuild.ARM]\r
# Stack for CPU Cores in Secure Monitor Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r