\r
// Motherboard Peripheral and On-chip peripheral\r
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000\r
#define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r
//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r
\r
//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r
#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r
\r
-// DRAM\r
-#define ARM_EB_DRAM_BASE 0x70000000\r
-#define ARM_EB_DRAM_SZ 0x10000000\r
-\r
// Logic Tile\r
#define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r
#define ARM_EB_LOGIC_TILE_SZ 0x40000000\r
*******************************************/\r
\r
// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
+#define ARM_EB_SYS_ID_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00000)\r
#define ARM_EB_SYS_OSC4_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)\r
#define ARM_EB_SYS_LOCK_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00020)\r
#define ARM_EB_SYS_100HZ_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00024)\r
#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_EB_SYS_RESETCTL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00040)\r
#define ARM_EB_SYS_CLCD_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
-#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
-#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
-#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
\r
// SP810 Controller\r
#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
// SYSTRCL Register\r
#define ARM_EB_SYSCTRL 0x10001000\r
\r
-// Uart0\r
-#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
-\r
-// SP804 Timer Bases\r
-#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
-#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
-#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
-#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
-\r
// Dynamic Memory Controller Base\r
-#define ARM_EB_DMC_BASE 0x10018000\r
+#define ARM_EB_DMC_BASE 0x10018000\r
\r
// Static Memory Controller Base\r
-#define ARM_EB_SMC_CTRL_BASE 0x10080000\r
-#define PL111_CLCD_BASE 0x10020000\r
+#define ARM_EB_SMC_CTRL_BASE 0x10080000\r
+\r
//Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work\r
#define PL111_CLCD_VRAM_BASE 0x00100000\r
\r
// L2x0 Cache Controller Base Address\r
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
\r
+#define ARM_EB_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)\r
+#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (UINT32)(0x0EU << 24)\r
+#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)\r
\r
/*******************************************\r
-// Interrupt Map\r
+// System Configuration Control\r
*******************************************/\r
\r
-// Timer Interrupts\r
-#define TIMER01_INTERRUPT_NUM 34\r
-#define TIMER23_INTERRUPT_NUM 35\r
-\r
-\r
-/*******************************************\r
-// EFI Memory Map in Permanent Memory (DRAM)\r
-*******************************************/\r
+// Sites where the peripheral is fitted\r
+#define ARM_EB_UNSUPPORTED ~0\r
\r
-// This region is allocated at the bottom of the DRAM. It will be used\r
-// for fixed address allocations such as Vector Table\r
-#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
+#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))\r
\r
-// This region is the memory declared to PEI as permanent memory for PEI\r
-// and DXE. EFI stacks and heaps will be declared in this region.\r
-#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000\r
+#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_EB_UNSUPPORTED,1)\r
\r
#endif \r