// DRAM\r
#define ARM_VE_DRAM_BASE 0x60000000\r
#define ARM_VE_DRAM_SZ 0x40000000\r
+// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
+#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
\r
// External AXI between daughterboards (Logic Tile)\r
#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
// PL310 L2x0 Cache Controller Base Address\r
//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
\r
+/***********************************************************************************\r
+ Select between Motherboard and Core Tile peripherals\r
+************************************************************************************/\r
+\r
+// Specify which PL111 to use\r
+//#define PL111_CLCD_BASE PL111_CLCD_MOTHERBOARD_BASE\r
+#define PL111_CLCD_BASE PL111_CLCD_CORE_TILE_BASE\r
+\r
/***********************************************************************************\r
Peripherals' misc settings\r
************************************************************************************/\r
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
\r
\r
+// PL111 Lcd\r
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
+\r
/***********************************************************************************\r
// Interrupt Map\r
************************************************************************************/\r