/** @file\r
* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
************************************************************************************/\r
\r
// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
+#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)\r
+#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)\r
#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r
#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r
+#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)\r
+#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)\r
#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
\r
// SP810 Controller\r
+#ifndef SP810_CTRL_BASE\r
#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
-\r
-// Uart0\r
-#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
-\r
-// SP805 Watchdog on motherboard\r
-#define SP805_WDOG_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)\r
-\r
-// SP804 Timer Bases\r
-#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
-#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
-#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
-#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
-\r
-// PL031 Real Time Clock\r
-#define PL031_RTC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x17000)\r
+#endif\r
\r
// PL111 Colour LCD Controller - motherboard\r
#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r
// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r
\r
-#define ARM_VE_SYS_PROC_ID_MASK (0xFF << 24)\r
-#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (0xFF << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (0x12 << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (0x14 << 24)\r
-\r
+#define ARM_VE_SYS_PROC_ID_HBI 0xFFF\r
+#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)\r
+#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A7 (UINT32)(0x18U << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A12 (UINT32)(0x1CU << 24)\r
+\r
+// Boot Master Select:\r
+// 0 = Site 1 boot master\r
+// 1 = Site 2 boot master\r
+#define ARM_VE_SYS_MISC_MASTERSITE (1 << 14)\r
//\r
// Sites where the peripheral is fitted\r
//\r
// Can not access the battery backed-up hardware clock on the Versatile Express motherboard\r
#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)\r
\r
+//\r
+// System ID\r
+//\r
+// All RTSM VE models have the same System ID : 0x225F500\r
+//\r
+// FVP models have a different System ID.\r
+// Default Base model System ID : 0x00201100\r
+// [31:28] Rev - Board revision: 0x0 = Rev A\r
+// [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform\r
+// [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)\r
+// [11:8] Plat - Platform type: 0x1 = Model\r
+// [7:0] FPGA - FPGA build, BCD coded: 0x00\r
+//\r
+//HBI = 010 = Foundation Model\r
+//HBI = 020 = Base Platform\r
+//\r
+// And specifically, the GIC register banks start at the following\r
+// addresses:\r
+// Variant = 0 Variant = 1\r
+//GICD 0x2c001000 0x2f000000\r
+//GICC 0x2c002000 0x2c000000\r
+//GICH 0x2c004000 0x2c010000\r
+//GICV 0x2c006000 0x2c020000\r
+\r
+#define ARM_FVP_BASE_BOARD_SYS_ID (0x00200100)\r
+#define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)\r
+\r
+#define ARM_FVP_SYS_ID_REV_MASK (UINT32)(0xFUL << 28)\r
+#define ARM_FVP_SYS_ID_HBI_MASK (UINT32)(0xFFFUL << 16)\r
+#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)\r
+#define ARM_FVP_SYS_ID_PLAT_MASK (UINT32)(0xFUL << 8 )\r
+#define ARM_FVP_SYS_ID_FPGA_MASK (UINT32)(0xFFUL << 0 )\r
+#define ARM_FVP_GIC_VE_MMAP 0x0\r
+#define ARM_FVP_GIC_BASE_MMAP (UINT32)(1 << 12)\r
+\r
+// The default SYS_IDs. These can be changed when starting the model.\r
+#define ARM_RTSM_SYS_ID (0x225F500)\r
+#define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)\r
+#define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)\r
+\r
#endif /* VEXPRESSMOTHERBOARD_H_ */\r
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