ArmPlatformPkg/ArmVExpress-CTA15-A7: Added support for CoreTile Express A15x2_A7x3

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA15-A7 / CTA15-A7.c

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c
new file mode 100644 (file)
index 0000000..c650a6e
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c
@@ -0,0 +1,193 @@
+/** @file\r
+*\r
+*  Copyright (c) 2012, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {\r
+  {\r
+    // Cluster 0, Core 0\r
+    0x0, 0x0,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
+    (UINT64)0\r
+  },\r
+  {\r
+    // Cluster 0, Core 1\r
+    0x0, 0x1,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
+    (UINT64)0\r
+  },\r
+#ifndef ARM_BIGLITTLE_TC2\r
+  {\r
+    // Cluster 0, Core 2\r
+    0x0, 0x2,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
+    (UINT64)0\r
+  },\r
+  {\r
+    // Cluster 0, Core 3\r
+    0x0, 0x3,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
+    (UINT64)0\r
+  },\r
+#endif\r
+  {\r
+    // Cluster 1, Core 0\r
+    0x1, 0x0,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
+    (UINT64)0\r
+  },\r
+  {\r
+    // Cluster 1, Core 1\r
+    0x1, 0x1,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
+    (UINT64)0\r
+  },\r
+  {\r
+    // Cluster 1, Core 2\r
+    0x1, 0x2,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
+    (UINT64)0\r
+  }\r
+#ifndef ARM_BIGLITTLE_TC2\r
+  ,{\r
+    // Cluster 1, Core 3\r
+    0x1, 0x3,\r
+\r
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
+    (UINT64)0\r
+  }\r
+#endif\r
+};\r
+\r
+/**\r
+  Return the current Boot Mode\r
+\r
+  This function returns the boot reason on the platform\r
+\r
+  @return   Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+  VOID\r
+  )\r
+{\r
+  return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+  Initialize controllers that must setup in the normal world\r
+\r
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
+  in the PEI phase.\r
+\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+  IN  UINTN                     MpId\r
+  )\r
+{\r
+  if (!IS_PRIMARY_CORE(MpId)) {\r
+    return RETURN_SUCCESS;\r
+  }\r
+\r
+  // Nothing to do here\r
+\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Initialize the system (or sometimes called permanent) memory\r
+\r
+  This memory is generally represented by the DRAM.\r
+\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+EFI_STATUS\r
+PrePeiCoreGetMpCoreInfo (\r
+  OUT UINTN                   *CoreCount,\r
+  OUT ARM_CORE_INFO           **ArmCoreTable\r
+  )\r
+{\r
+  // Only support one cluster\r
+  *CoreCount    = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);\r
+  *ArmCoreTable = mVersatileExpressCTA15A7InfoTable;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+    &mArmMpCoreInfoPpiGuid,\r
+    &mMpCoreInfoPpi\r
+  }\r
+};\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+  OUT UINTN                   *PpiListSize,\r
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList\r
+  )\r
+{\r
+  *PpiListSize = sizeof(gPlatformPpiTable);\r
+  *PpiList = gPlatformPpiTable;\r
+}\r