Serial I/O Port library functions with no library constructor/destructor\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <Drivers/PL011Uart.h>\r
\r
+//\r
+// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only\r
+// control bit that is not supported.\r
+//\r
+STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
+\r
/*\r
\r
Initialise the serial port to the specified settings.\r
\r
LineControl = 0;\r
\r
- // The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept\r
+ // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept\r
// 1 char buffer as the minimum fifo size. Because everything can be rounded down,\r
// there is no maximum fifo size.\r
if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= 32)) {\r
LineControl |= PL011_UARTLCR_H_FEN;\r
- *ReceiveFifoDepth = 32;\r
+ if (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) > PL011_VER_R1P4)\r
+ *ReceiveFifoDepth = 32;\r
+ else\r
+ *ReceiveFifoDepth = 16;\r
} else {\r
ASSERT (*ReceiveFifoDepth < 32);\r
// Nothing else to do. 1 byte fifo is default.\r
}\r
\r
/**\r
- Set the serial device control bits.\r
-\r
- @param UartBase The base address of the PL011 UART.\r
- @param Control Control bits which are to be set on the serial device.\r
\r
- @retval EFI_SUCCESS The new control bits were set on the serial device.\r
- @retval EFI_UNSUPPORTED The serial device does not support this operation.\r
- @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+ Assert or deassert the control signals on a serial port.\r
+ The following control signals are set according their bit settings :\r
+ . Request to Send\r
+ . Data Terminal Ready\r
+\r
+ @param[in] UartBase UART registers base address\r
+ @param[in] Control The following bits are taken into account :\r
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
+ "Request To Send" control signal if this bit is\r
+ equal to one/zero.\r
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
+ the "Data Terminal Ready" control signal if this\r
+ bit is equal to one/zero.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
+ the hardware loopback if this bit is equal to\r
+ one/zero.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
+ disable the hardware flow control based on CTS (Clear\r
+ To Send) and RTS (Ready To Send) control signals.\r
+\r
+ @retval RETURN_SUCCESS The new control bits were set on the serial device.\r
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartSetControl (\r
- IN UINTN UartBase,\r
- IN UINT32 Control\r
+ IN UINTN UartBase,\r
+ IN UINT32 Control\r
)\r
{\r
- UINT32 Bits;\r
- UINT32 ValidControlBits;\r
-\r
- ValidControlBits = ( EFI_SERIAL_REQUEST_TO_SEND\r
- | EFI_SERIAL_DATA_TERMINAL_READY\r
- // | EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE // Not implemented yet.\r
- // | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE // Not implemented yet.\r
- | EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE\r
- );\r
-\r
- if (Control & (~ValidControlBits)) {\r
- return EFI_UNSUPPORTED;\r
+ UINT32 Bits;\r
+\r
+ if (Control & (mInvalidControlBits)) {\r
+ return RETURN_UNSUPPORTED;\r
}\r
\r
Bits = MmioRead32 (UartBase + UARTCR);\r
\r
if (Control & EFI_SERIAL_REQUEST_TO_SEND) {\r
Bits |= PL011_UARTCR_RTS;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_RTS;\r
}\r
\r
if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {\r
Bits |= PL011_UARTCR_DTR;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_DTR;\r
}\r
\r
if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {\r
Bits |= PL011_UARTCR_LBE;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_LBE;\r
}\r
\r
if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {\r
- Bits |= (PL011_UARTCR_CTSEN & PL011_UARTCR_RTSEN);\r
+ Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r
+ } else {\r
+ Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r
}\r
\r
MmioWrite32 (UartBase + UARTCR, Bits);\r
}\r
\r
/**\r
- Get the serial device control bits.\r
-\r
- @param UartBase The base address of the PL011 UART.\r
- @param Control Control signals read from the serial device.\r
\r
- @retval EFI_SUCCESS The control bits were read from the serial device.\r
- @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+ Retrieve the status of the control bits on a serial device.\r
+\r
+ @param[in] UartBase UART registers base address\r
+ @param[out] Control Status of the control bits on a serial device :\r
+\r
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY,\r
+ EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT,\r
+ EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY\r
+ are all related to the DTE (Data Terminal Equipment) and\r
+ DCE (Data Communication Equipment) modes of operation of\r
+ the serial device.\r
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive\r
+ buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit\r
+ buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the\r
+ hardware loopback is enabled (the ouput feeds the receive\r
+ buffer), 0 otherwise.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a\r
+ loopback is accomplished by software, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the\r
+ hardware flow control based on CTS (Clear To Send) and RTS\r
+ (Ready To Send) control signals is enabled, 0 otherwise.\r
+\r
+ @retval RETURN_SUCCESS The control bits were read from the serial device.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartGetControl (\r
- IN UINTN UartBase,\r
- OUT UINT32 *Control\r
+ IN UINTN UartBase,\r
+ OUT UINT32 *Control\r
)\r
{\r
UINT32 FlagRegister;\r
*Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;\r
}\r
\r
- if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
+ if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))\r
+ == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;\r
}\r
\r
-#ifdef NEVER\r
- // ToDo: Implement EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE\r
if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {\r
*Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;\r
}\r
\r
- // ToDo: Implement EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE\r
- if (SoftwareLoopbackEnable) {\r
- *Control |= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
- }\r
-#endif\r
-\r
return RETURN_SUCCESS;\r
}\r
\r
while (Buffer < Final) {\r
// Wait until UART able to accept another char\r
while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));\r
- \r
+\r
MmioWrite8 (UartBase + UARTDR, *Buffer++);\r
}\r
\r
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