This file implement the MMC Host Protocol for the ARM PrimeCell PL180.\r
\r
Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
- \r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
if ((Status & MCI_STATUS_CMD_ERROR)) {\r
// Clear Status register error flags\r
MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_ERROR);\r
- \r
+\r
if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));\r
RetVal = EFI_NO_RESPONSE;\r
// Read data from the RX FIFO\r
Loop = 0;\r
Finish = MMCI0_BLOCKLEN / 4;\r
- \r
+\r
// Raise the TPL at the highest level to disable Interrupts.\r
Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
\r
Loop++;\r
MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
Loop++;\r
- } else if ((Status & MCI_STATUS_CMD_TXFIFOEMPTY)) {\r
+ } else if (!(Status & MCI_STATUS_CMD_TXFIFOFULL)) {\r
MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
Loop++;\r
} else {\r
EFI_STATUS Status;\r
EFI_HANDLE Handle;\r
\r
+ DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL180\n",\r
+ MCI_PERIPH_ID_REG0));\r
+\r
+ // Check if this is a PL180\r
+ if (MmioRead8 (MCI_PERIPH_ID_REG0) != MCI_PERIPH_ID0 ||\r
+ MmioRead8 (MCI_PERIPH_ID_REG1) != MCI_PERIPH_ID1 ||\r
+ MmioRead8 (MCI_PERIPH_ID_REG2) != MCI_PERIPH_ID2 ||\r
+ MmioRead8 (MCI_PERIPH_ID_REG3) != MCI_PERIPH_ID3 ||\r
+ MmioRead8 (MCI_PCELL_ID_REG0) != MCI_PCELL_ID0 ||\r
+ MmioRead8 (MCI_PCELL_ID_REG1) != MCI_PCELL_ID1 ||\r
+ MmioRead8 (MCI_PCELL_ID_REG2) != MCI_PCELL_ID2 ||\r
+ MmioRead8 (MCI_PCELL_ID_REG3) != MCI_PCELL_ID3) {\r
+\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
Handle = NULL;\r
\r
MCI_TRACE ("PL180MciDxeInitialize()");\r
\r
//Publish Component Name, BlockIO protocol interfaces\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
- &Handle, \r
+ &Handle,\r
&gEfiMmcHostProtocolGuid, &gMciHost,\r
NULL\r
);\r