ArmPlatformPkg: remove unused PL301Axi driver

[mirror_edk2.git] / ArmPlatformPkg / Drivers / PL301Axi / PL301Axi.c

diff --git a/ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.c b/ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.c
deleted file mode 100644 (file)
index 8600721..0000000
--- a/ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials\r
-*  are licensed and made available under the terms and conditions of the BSD License\r
-*  which accompanies this distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#define PL301_QOS_TIDEMARK_MI_0                  0x400\r
-#define PL301_QOS_ACCESSCONTROL_MI_0             0x404\r
-\r
-#define PL301_QOS_TIDEMARK_MI_1                  0x420\r
-#define PL301_QOS_ACCESSCONTROL_MI_1             0x424\r
-\r
-#define PL301_QOS_TIDEMARK_MI_2                  0x440\r
-#define PL301_QOS_ACCESSCONTROL_MI_2             0x444\r
-\r
-#define PL301_AR_ARB_MI_0                        0x408\r
-#define PL301_AW_ARB_MI_0                        0x40C\r
-\r
-#define PL301_AR_ARB_MI_1                        0x428\r
-#define PL301_AW_ARB_MI_1                        0x42C\r
-\r
-#define PL301_AR_ARB_MI_2                        0x448\r
-#define PL301_AW_ARB_MI_2                        0x44C\r
-\r
-#define PL301_MI_1_OFFSET                        0x20\r
-#define PL301_MI_2_OFFSET                        0x40\r
-#define PL301_MI_3_OFFSET                        0x60\r
-#define PL301_MI_4_OFFSET                        0x80\r
-#define PL301_MI_5_OFFSET                        0xa0\r
-\r
-#define V2P_CA9_FAXI_MI0_TIDEMARK_VAL            0x6\r
-#define V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL         0x1\r
-\r
-#define V2P_CA9_FAXI_MI1_TIDEMARK_VAL            0x6\r
-#define V2P_CA9_FAXI_MI1_ACCESSCNTRL_VAL         0x1\r
-\r
-#define V2P_CA9_FAXI_MI2_TIDEMARK_VAL            0x6\r
-#define V2P_CA9_FAXI_MI2_ACCESSCNTRL_VAL         0x1\r
-\r
-\r
-#define FAxiWriteReg(reg,val)                    MmioWrite32(FAxiBase + reg, val)\r
-#define FAxiReadReg(reg)                         MmioRead32(FAxiBase + reg)\r
-\r
-// IN FAxiBase\r
-// Initialize PL301 Dynamic Memory Controller\r
-VOID PL301AxiInit(UINTN FAxiBase) {\r
-    // Configure Tidemark Register for Master Port 0 (MI 0)\r
-    FAxiWriteReg(PL301_QOS_TIDEMARK_MI_0, V2P_CA9_FAXI_MI0_TIDEMARK_VAL);\r
-\r
-    // Configure the Access Control Register (MI 0)\r
-    FAxiWriteReg(PL301_QOS_ACCESSCONTROL_MI_0, V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL);\r
-\r
-    // MP0\r
-    // Set priority for Read\r
-    FAxiWriteReg(PL301_AR_ARB_MI_0, 0x00000100);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_0, 0x01000200);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_0, 0x02000200);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_0, 0x03000200);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_0, 0x04000200);\r
-\r
-    // Set priority for Write\r
-    FAxiWriteReg(PL301_AW_ARB_MI_0, 0x00000100);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_0, 0x01000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_0, 0x02000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_0, 0x03000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_0, 0x04000200);\r
-\r
-    // MP1\r
-    // Set priority for Read\r
-    FAxiWriteReg(PL301_AR_ARB_MI_1, 0x00000100);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_1, 0x01000200);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_1, 0x02000200);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_1, 0x03000200);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_1, 0x04000200);\r
-\r
-    // Set priority for Write\r
-    FAxiWriteReg(PL301_AW_ARB_MI_1, 0x00000100);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_1, 0x01000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_1, 0x02000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_1, 0x03000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_1, 0x04000200);\r
-\r
-    // MP2\r
-    // Set priority for Read\r
-    FAxiWriteReg(PL301_AR_ARB_MI_2, 0x00000100);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_2, 0x01000100);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_2, 0x02000100);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_2, 0x03000100);\r
-    FAxiWriteReg(PL301_AR_ARB_MI_2, 0x04000100);\r
-\r
-    // Set priority for Write\r
-    FAxiWriteReg(PL301_AW_ARB_MI_2, 0x00000100);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_2, 0x01000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_2, 0x02000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_2, 0x03000200);\r
-    FAxiWriteReg(PL301_AW_ARB_MI_2, 0x04000200);\r
-}\r