//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
.align 3\r
\r
GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word CEntryPoint\r
\r
ASM_PFX(_ModuleEntryPoint):\r
+ // Do early platform specific actions\r
+ bl ASM_PFX(ArmPlatformPeiBootAction)\r
+\r
// Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
- \r
+ // Keep a copy of the MpId register value\r
+ mov r5, r0\r
+\r
+ // Is it the Primary Core ?\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+\r
// Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
add r1, r1, r2\r
\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
+ // r0 is equal to 1 if I am the primary core\r
+ cmp r0, #1\r
beq _SetupPrimaryCoreStack\r
\r
_SetupSecondaryCoreStack:\r
// r1 contains the base of the secondary stacks\r
\r
- // Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
+ // Get the Core Position\r
+ mov r6, r1 // Save base of the secondary stacks\r
+ mov r0, r5\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
add r0, r0, #1\r
\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
mul r0, r0, r2\r
// SP = StackBase + StackOffset\r
- add sp, r1, r0\r
+ add sp, r6, r0\r
\r
_PrepareArguments:\r
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r